Cirrus Logic EP73xx - Manual (Page 17)

EP7309/11/12 User’s Manual - DS508UM4 1-3
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Copyright Cirrus Logic, Inc. 2003
Introduction
11
1
Internal Register Map
Table 1-2 on page 1-4 shows the Internal Registers of the EP73xx when the CPU is
configured to a little endian memory system. Table 1-3 on page 1-6 shows the
differences that occur when the CPU is configured to a big endian memory system for
byte-wide access to Ports A, B, and D. All the internal registers are inherently little
endian (i.e., the least significant byte is attached to bits 7 to 0 of the data bus). Hence,
the system Endianness affects the addresses required for byte accesses to the internal
registers, resulting in a reversal of the byte address required to read/write a
particular byte within a register.
There is no effect on the register addresses for word accesses. Bits A[0-1] of the
internal address bus are only decoded for Ports A, B, and D (to allow read/write to
individual ports). For all other registers, bits
A[0-1] are not decoded, so that byte reads
will return the whole register contents onto the EP73xx’s internal bus, from where the
appropriate byte (according to the endianness) will be read by the CPU. To avoid the
additional complexity, it is preferable to perform all internal register accesses as word
operations, except for ports A to D which are explicitly designed to operate with byte
accesses, as well as with word accesses.
An 8 Kbytes segment of memory in the range 0x8000.0000 to 0x8000.3FFF is reserved
for internal use in the EP73xx. Accesses in this range will not cause any external bus
activity unless debug mode is enabled. Writes to bits that are not explicitly defined in
the internal area are legal and will have no effect. Reads from bits not explicitly
defined in the internal area are legal but will read undefined values. All the internal
addresses should only be accessed as 32-bit words and are always on a word
boundary, except for the GPIO port registers, which can be accessed as bytes. Address
bits in the range
A[0-5] are not decoded (except for Ports A–D), this means each
internal register is valid for 64 bytes (i.e., the SYSFLG1 register appears at locations
0x8000.0140 to 0x8000.017C). There are some gaps in the register map for backward
compatibility reasons, but registers located next to a gap are still only decoded for
64 bytes.
The GPIO port registers are byte-wide and can be accessed as a word but not as a half-
word. These registers additionally decode
A[0-1] . All addresses are in hexadecimal
notation.
0x8000.4000 Unused ~1 Gbyte
0x8000.0000 Internal registers 8 Kbytes
0x7000.0000 Boot ROM (nCS[7]) 128 bytes
0x6000.0000 SRAM (nCS[6]) 48 Kbytes
0x5000.0000 Expansion (nCS[5]) 256 Mbytes
0x4000.0000 Expansion (nCS[4]) 256 Mbytes
0x3000.0000 Expansion (nCS[3]) 256 Mbytes
0x2000.0000 Expansion (nCS[2]) 256 Mbytes
0x1000.0000 ROM Bank 1 (nCS[1]) 256 Mbytes
0x0000.0000 ROM Bank 0 (nCS[0]) 256 Mbytes
Table 1-1: EP73xx Memory Map in External Boot Mode (Continued)
Address Contents Size