Cirrus Logic EP73xx - Manual (Page 51)

EP7309/11/12 User’s Manual - DS508UM4 4-5
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Copyright Cirrus Logic, Inc. 2003
Interrupt Controller
44
4
Interrupt Listing
Table 4-4 , Table 4-5 , and Table 4-6 show the names and allocation of interrupts in the
EP73xx.
Table 4-4: Interrupt Allocation in the First Interrupt Register
Interrupt
Bit in INTMR1
and INTSR1
Name Comment
FIQ 0 EXTFIQ External fast interrupt input (nEXTFIQ pin)
FIQ 1 BLINT Battery low interrupt
FIQ 2 WEINT Tick Watchdog expired interrupt
FIQ 3 MCINT Media changed interrupt
IRQ 4 CSINT CODEC sound interrupt
IRQ 5 EINT1 External interrupt input 1 (nEINT[1] pin)
IRQ 6 EINT2 External interrupt input 2 (nEINT[2] pin)
IRQ 7 EINT3 External interrupt input 3 (EINT[3] pin)
IRQ 8 TC1OI TC1 underflow interrupt
IRQ 9 TC2OI TC2 underflow interrupt
IRQ 10 RTCMI RTC compare match interrupt
IRQ 11 TINT 64 Hz tick interrupt
IRQ 12 UTXINT1 Internal UART1 transmit FIFO empty interrupt
IRQ 13 URXINT1 Internal UART1 receive FIFO full interrupt
IRQ 14 UMSINT Internal UART1 modem status changed interrupt
IRQ 15 SSEOTI Synchronous serial interface 1 end of transfer interrupt
Table 4-5: Interrupt Allocation in the Second Interrupt Register
Interrupt
Bit in INTMR2 and
INTSR2
Name Comment
IRQ 0 KBDINT Key press interrupt
IRQ 1 SS2RX Master / slave SSI 16 bytes received
IRQ 2 SS2TX Master / slave SSI 16 bytes transmitted
IRQ 12 UTXINT2 UART2 transmit FIFO empty interrupt
IRQ 13 URXINT2 UART2 receive FIFO full interrupt
Table 4-6: Interrupt Allocation in the Third Interrupt Register
Interrupt
Bit in INTMR3 and
INTSR3
Name Comment
FIQ 0 DAIINT DAI interface interrupt