Cirrus Logic EP73xx - Manual (Page 150)

17-4 EP7309/11/12 User’s Manual - DS508UM4
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Copyright Cirrus Logic, Inc. 2003
UART and SIR Encoder
17
enabled) is half-empty. Same condition applies during transmit if the FIFOs are not
enabled. An interrupt will be generated when there is no data in the UART holding
register. The third interrupt is the modem interrupt UMSINT and will be active if
either the two modem status lines (CTS or DTS) change state
SIR Encoder
UART1 shares its FIFOs with an IrDA (Infrared Data Association) SIR protocol
encoder. This encoder can be enabled from SYSCON1 at SIREN (bit 15). UART1 must
be enabled for the encoder to work. Data is sent and received by the encoder using
the UART data holding register. The SIR and UART1 share the same data holding
register and FIF0s. Once the SIR encoder is enabled, is controls UART1.
The SIR encoder output pin is LEDDRV and input is received from PHDIN . The modem
lines can still cause an interrupt irrespective of the SIR activity and can be masked if
necessary.
SYSCON1 bit 20 controls the encoding strategy for transmitting zeros in the bit
stream. A zero in this field can be represented by a pulse width of 3/16th of the bit
rate period or a pulse width of 3/16th of a 115.2k bit rate clock (regardless of selected
bit rate). Actual bit rate is selected by the UART1 bit rate clock.
UART2
UART2 supports only two interrupts, Rx and Tx in the same manner as UART1. It
does not possess the additional control lines CTS, DTS. UART2 is enabled in
SYSCON2 register bit 8.