Cirrus Logic EP73xx - Manual (Page 89)

EP7309/11/12 User’s Manual - DS508UM4 8-5
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Copyright Cirrus Logic, Inc. 2003
SRAM/Expansion Bus Controller
88
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SQAEN[6]: Sequential access enable. Setting this bit will enable the sequential
accesses that are on a quad word boundary to take advantage of
faster access times from devices that support page mode. The
sequential accesses will be faulted after four words (to allow video
refresh cycles to occur), even if the access is part of a longer
sequential access. In addition, when this bit is not set, non-
sequential accesses will have a single idle cycle inserted at least
every four cycles so that the chip select is de-asserted periodically
between accesses for easier debug.
CLKENB[7]: Expansion clock enable. Setting this bit enables the EXPCLK to be
active during accesses to the selected expansion device. This will
provide a timing reference for devices that need to extend bus
cycles using the
EXPRDY input. Back-to-back (but not necessarily
page mode) accesses will result in a continuous clock. This bit will
only affect
EXPCLK when the PLL is being used (i.e., in 73.728-
18.432 MHz mode.) When operating in 13 MHz mode, the
EXPCLK pin is an input, so it is not affected by this register bit. To
saver power internally, it should always be set to zero when
operating at 13 MHz mode.
Memory Configuration Register 2 (MEMCFG2)
Address: 0x8000.01C0, Read / Write
Definition: See “Memory Configuration Register 1 (MEMCFG1)” details for
programming the remaining chip selects. Same programming
features and requirements apply.
Note: CS6 and CS7 are not configurable.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
nCS[7] Configuration nCS[6] Configuration
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
nCS[5] Configuration nCS[4] Configuration