Cirrus Logic EP73xx - Manual (Page 148)

17-2 EP7309/11/12 User’s Manual - DS508UM4
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Copyright Cirrus Logic, Inc. 2003
UART and SIR Encoder
17
;
ldr r1, =UART1
str r1, [r12, #0x04C0] ; UART1 Configured 0x8000.04C0
ldr r1, =UART1EN
ldr r0, [r12, #0x100]
orr r0, r0, r1 ; Set UART1EN bit
str r0, [r12, #0x100] ; Store to SYSCON1 0x8000.0100
;
Operational Overview
Both UARTs offer similar functionality to National Semiconductor’s 16C550A device
and can support bit rates of up to 115.2 kbps. Each one includes two 16-byte FIFOs
used for transmit and receive data.
Baud rates are frequency dependent. When operating from the internal PLL, the
interface supports various baud rates from 115.2 kbps downwards. When operating
from 13 MHz external clock source, the baud rates generated will have a slight error
which will be less than or equal to 0.75%.The baud rates attainable with the 13 MHz
external clock include: 9.6,19.2,38,58, and 115.2 kbps.
Interrupts for both UARTs can be created by setting the appropriate bits in the
INTMR1 and INTMR2 registers. The INTSR1 and INTSR2 status register will show
cause of interrupt and clearing the interrupt requires filling the FIFOs to at least half
full.
Because the UARTs derive their baud rates from the PLL, operation at a CPU speed of
90 MHz will cause an upward shifting of effective baud rates. Using the divisors
available, most baud rates can be achieved within a 2% deviation of legal rates. This
should not be a problem since most UARTs work within a
± 2% deviation. Table 17-2
shows specific divisors and deviation information for UARTs at 90 MHz. Table 17-3 on
page 17-3 and Table 17-4 on page 17-3 describe the UART bit rates in PLL Clock Mode
and 13 MHz Clock Mode, respectively.
Table 17-2: UART Bit Rates at 90 MHz
Bit Rate Divisor Value Error
57600 4 -2.00%
19200 14 -2.00%
14400 19 -2.00%
9600 28 1.38%
4800 58 -0.34%
2400 117 -0.34%
1200 234 0.09%
300 940 -0.02%
110 2565 -0.01%