Cirrus Logic EP73xx - Manual (Page 50)

4-4 EP7309/11/12 User’s Manual - DS508UM4
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Copyright Cirrus Logic, Inc. 2003
Interrupt Controller
4
Interrupt Types and Priorities
The EP73xx interrupt controller can generate two types of interrupts: Standard (IRQ)
or Fast (FIQ). Seventeen of the twenty-two interrupt sources are IRQ interrupts, while
the remaining five are FIQ. FIQs have a higher priority than IRQs. If two interrupts
are received from within the same group (IRQ or FIQ), the order in which they are
serviced must be resolved in software. The priorities are listed in
Table 4-3 .
Interrupt Operation
All interrupts are level sensitive; that is, they must conform to the following
sequence:
1. The interrupting device (either external or internal) asserts the appropriate
interrupt.
2. If the appropriate bit is set in the interrupt mask register, then either an FIQ
or an IRQ will be asserted by the interrupt controller. (Descriptions of each
bit in this register can be found in
“Interrupt Status Register 1 (INTSR1)”
on page 4-8 .)
3. If interrupts are enabled, the processor jumps to the appropriate address.
4. Within the interrupt handler routine, the status register is read to
determine if the source of the interrupt(s). This will determine which
subroutine(s) to call to service said interrupt(s).
5. Software in the interrupt service routine will clear the interrupt source by
an action specific to the device requesting the interrupt (i.e., reading the
UART RX register).
The interrupt service routine may then re-enable interrupts; other pending interrupts
are serviced in a similar way. Alternately, the service routine may return to the
interrupt dispatch code, which can check for pending interrupts and dispatch them
accordingly. The “End of Interrupt” type interrupts are latched. All other interrupt
sources (i.e., external interrupt source) must be held active until its respective service
routine starts executing. See
“End-Of-Interrupt Locations” on page 4-13 for more
details.
Table 4-3: Exception Priority Handling
Priority Exception
Highest Reset
. Data Abort
. FIQ
. IRQ
. Prefetch Abort
Lowest Undefined Instruction, Software Interrupt