Lcd register descriptions, Lcd control register (lcdcon), Lcd register descriptions -7 – Cirrus Logic EP73xx User Manual
Page 97: Lcd control register (lcdcon) -7
EP7309/11/12 User’s Manual - DS508UM4
9-7
Copyright Cirrus Logic, Inc. 2003
LCD Interface
99
9
LCD Register Descriptions
LCD Control Register (LCDCON)
Address:
0x8000.02C0, Read / Write
Bit Descriptions:
Video Buffer Size [0:12]:Total number of bits in the video display buffer.
Formula: (Total bits in video buffer/128) - 1
ex. 640x240 LCD with 4 bits-per-pixel
Video Buffer: 640x240x4 = 614400
Video Buffer Size = (614400/128)-1 = 4799 or 0x12BF
Note: Minimum value for this field is 3.
Line Length[13:18]:Number of pixels in one complete line (row).
Formula: (Number of pixels per line/16) - 1
ex. 640x240 LCD
Line length = (640/16) - 1 = 39 or 0x27
Note: Minimum value for this field is 1.
Pixel Prescale[19:24]: Sets the pixel rate prescale and is always derived from
36 MHz clock when in PLL mode or 13 MHz when using the
external 13 MHz external crystal.
Pixel Prescale = ((CPU clock (Hz))/(Refresh Rate x Total pixels) - 1
Pixel Rate = (CPU Clock (MHz)/(Pixel Prescale + 1)
ex. 640x240 in PLL mode(18-74 MHz CPU clock). 70 Hz refresh
rate is desired.
Pixel Prescale = (36x10
6
)/(70x640x240) - 1 = 2.428 or 2 (round
down)
Pixel rate = (36x10
6
)/((2 + 1) = 12.288 MHz so the actual refresh
rate is: 12.288x10
6
/(640x240) = 80 Hz
Note: If the EP73xx is running at 90 MHz, the data bus rate would increase from 36 to
45 MHz.
AC prescale[24:19]: Sets the LCD AC bias frequency. This frequency is the
required AC bias frequency for a given manufacturer’s LCD plate.
it is derived from the frequency of the line clock (CL[1]). The LCD
M signal will toggle after n+1 counts of the line clock where is M
is the number programmed into this field.
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
GSMD
GSEN
AC Prescale
Pixel Prescale
Line
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Length
VIdeo Buffer Size