Cirrus Logic EP73xx - Manual (Page 44)

3-2 EP7309/11/12 User’s Manual - DS508UM4
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Copyright Cirrus Logic, Inc. 2003
Timers
3
str r1, [r12, #0x0100] ; Prescale - 2 kHz clock
ldr r1, =TC1Timer
str r1, [r12, #0x300] ; 10 ms timer rate
ldr r0, =TC1Mask
str r0, [r12,#0x0280] ; Interrupt enabled
;
Operational Overview
These identical count-down timers derive their clock from the internal PLL or
external 13 MHz clock. Values for these timers are programmed into the read/write
registers as seen below and are decremented on the second active edge of the clock
once the write to the register is complete (i.e., after the first complete period of the
clock). When the timer reaches 0, the corresponding interrupt is asserted (if enabled).
Values can be written to the data registers at any time.
When running from the PLL clock, 512 kHz and 2 kHz rates are possible for each
timer. When using the external 13 MHz crystal, the default frequencies for the timers
will be 541 and 2.115 kHz. Optionally, in 13 MHz mode, a divider of 26 can be used to
generate a frequency of 500 kHz. This is set automatically in 13 MHz mode by setting
the OSTB bit in SYSCON2 register thus routing a 500 kHz clock to the timer. This
however, does not affect the frequencies derived for any of the other internal
peripherals.
Setting the clock source frequency for TC1 and TC2 involves writes to SYSCON1 bit 5
and 7. Clearing each bit sets the clock to 2 kHz. Setting this bit sets the clock at
512 kHz.
Interrupts masks for these registers are set in the INTMR1 register and status seen in
the INTSR1 register. To clear the interrupt for TC1 and TC2, a write to the TE2EOI-
TC1 and TE2EOI-TC2 registers respectively will clear the underflow interrupt.
When operating at 90 Mhz, the two timers deriving their clocks from the PLL will be
shifted upwards by 22.5%. Therefore the 512 kHz clock will become 627.2 kHz and
the 2 kHz clock will become 2.45 kHz. The timer deriving its clock from the RTC is not
affected.
Free Running Mode
In free running mode, the counter will wrap around to 0xFFFF when it underflows
and will continue to count down. Any value written will be decremented on the
second edge of the selected clock rate. A value of 0 in bit 4 or 6 of SYSCON1 will set
free running mode for TC1 and TC2 respectively.