Programming the dai control and data registers – Cirrus Logic EP73xx User Manual
Page 130
16-6
EP7309/11/12 User’s Manual - DS508UM4
Copyright Cirrus Logic, Inc. 2003
DAI/CODEC/SSI2
16
*
+0.23% Sample Frequency Error
**
Optional 12.288 MHz external clock
MCLK(BUZ)
will always output 256 Fs on pin 93 for internal or external clocks used.
MCLK(BUZ) is also referred to as MCLKOUT in the datasheet. For details on the
hardware interface for the DAI and creating MCLK for external CODECs, please refer
to application note
Programming the DAI Control and Data Registers
Once the DAI machine has been selected (DAI64FS register), the mode(128/64 Fs)
must be determined based on the external CODECs used. If 64 Fs is selected, 128 Fs
must be deselected. The converse is also required. The register 64DAIFS enables
128/64 Fs mode along with SYSCON3. Both registers must be programmed to set or
clear these options.
In 64 Fs mode, the ECS bit in the DAIR control register must be set regardless of the
source for
MCLK
. For 128 Fs, the bit is not read.
For both modes, the 64DAIFS register will always select the audio clock source and
program the audio divider. See the register tables for more information. Details for
programming the DAI FIFOs and interrupts for digital audio applications can be
found in application note
The DAI FIFOs in the DAIDR2 register must be enabled and to generate an interrupt
based on the condition of the FIFOs, the DAIINT bit in the INTRM3 register must be
set along with the appropriate mask from the DAI Control Register. This will insure
an FIQ interrupt will occur. The interrupt can be cleared by writing 0xFFFFFFFF to
the DAISR register.
Table 16-6: Programmable Audio Divisors at 90 MHz
Clock
Source (MHz)
Sample
Frequency (kHz)
128 Fs
Audio Bit Clock
(MHz)
64 Fs
Audio Bit Clock
(MHz)
128/64 Fs
Divisor
(AUDIV)
*
90.3168
8
1.024
0.512
44
*
90.3168
11.025
1.4112
0.7056
32
**
12.288
12
1.536
0.786
8
*
90.3168
16
2.048
1.024
22
*
90.3168
22.05
2.8224
1.4112
16
**
12.288
24
3.072
1.536
4
*
90.3168
32
4.096
2.048
11
*
90.3168
44.1
5.6448
2.8224
8
**
12.288
48
6.144
3.072
2