Cirrus Logic EP73xx - Manual (Page 137)

EP7309/11/12 User’s Manual - DS508UM4 16-13
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Copyright Cirrus Logic, Inc. 2003
DAI/CODEC/SSI2
1616
16
Full Bit Descriptions
DAIEN:
When the DAI is disabled, all of its clocks are powered down to minimize power
consumption. Note that DAIEN is the only control bit within the DAI interface that is
reset to a known state. It is cleared to zero to ensure the DAI timing is disabled
following a reset of the device.
When the DAI timing is enabled, SCLK begins to transition and the start of the first
frame is signaled by driving the LRCK pin low. The rising and falling-edge of LRCK
coincides with the rising and falling-edge of SCLK . As long as the DAIEN bit is set,
the DAI interface operates continuously, transmitting and receiving 128 bit data
frames. When the DAIEN bit is cleared, the DAI interface is disabled immediately,
causing the current frame which is being transmitted to be terminated. Clearing
DAIEN resets the DAI’s interface FIFOs. However DAI data register 2, the control
register, and the status register are not reset. Therefore, the user must ensure these
registers are properly reconfigured before re-enabling the DAI interface.
LCTM/LRCM/RCTM/RRCM:
The DAI interface can generate four maskable interrupts and four non-maskable
interrupts, as described in the sections below. Only one interrupt line is wired into the
interrupt controller for the whole DAI interface. This interrupt is the wired OR of all
eight interrupts (after masking where appropriate). The software servicing the
interrupts must read the status register in the DAI to determine which source(s)
caused the interrupt. It is possible to prevent any DAI sources causing an interrupt by
masking the DAI interrupt in the interrupt controller register.
LCTM:
The Left Channel Sample Transmit FIFO interrupt mask (LCTM) bit is used to mask
or enable the left channel sample transmit FIFO service request interrupt. When
LCTM = 0, the interrupt is masked and the state of the left channel Transmit FIFO
service request (LCTS) bit within the DAI status register is ignored by the interrupt
controller. When LCTM = 1, the interrupt is enabled and whenever LCTS is set (one)
an interrupt request is made to the interrupt controller. Note that programming
LCTM = 0 does not affect the current state of LCTS or the Left Channel Transmit FIFO
logic’s ability to set and clear LCTS; it only blocks the generation of the interrupt
request.
LCRM:
The Left Channel Sample Transmit FIFO interrupt mask (LCTM) bit is used to mask
or enable the left channel sample transmit FIFO service request interrupt. When
LATM = 0, the interrupt is masked and the state of the Left Channel Transmit FIFO
service request (LCTS) bit within the DAI status register is ignored by the interrupt
controller. When LCTM = 1, the interrupt is enabled and whenever LCTS is set (one)
an interrupt request is made to the interrupt controller. Note that programming
LCTM = 0 does not affect the current state of LCTS or the Left Channel Transmit FIFO
logic’s ability to set and clear LCTS; it only blocks the generation of the interrupt
request.