System flag register 2 (sysflg2), System flag register 2 (sysflg2) -12, Input, latched during – Cirrus Logic EP73xx User Manual

Page 72

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5-12

EP7309/11/12 User’s Manual - DS508UM4

Copyright Cirrus Logic, Inc. 2003

System Registers

5

System Flag Register 2 (SYSFLG2)

Address:

0x8000.1140, Read Only

Definition:

The SYSFLG2 system flag register is a 32-bit read only register. It
provides information regarding the status of the CPU and associated
peripherals.

Bit Descriptions:

SS2RXOF: Master/slave SSI2 RX FIFO overflow. This bit is set when a write

is attempted to a full RX FIFO (i.e., when RX is still receiving data
and the FIFO is full). This can be cleared in one of two ways:

1) Empty the FIFO (remove data from FIFO) and then

write to

SRXEOF location.

2) Disable the RX (affects of disabling the RX will not take

place until a full SSI2 clock cycle after it is disabled)

RESVAL:

Master/slave SSI2 RX FIFO residual byte present, cleared by
popping the residual byte into the SSI2 RX FIFO or by a new RX
frame sync pulse.

RESFRM:

Master/slave SSI2 RX FIFO residual byte present, cleared only by
a new RX frame sync pulse.

SS2RXFE: Master/slave SSI2 RX FIFO empty bit. This will be set if the

16 x 16 RX FIFO is empty.

SS2TXFF:

Master/slave SSI2 TX FIFO full bit. This will be set if the 16 x 16
TX FIFO is full. This will get cleared when data is removed from
the FIFO or the EP73xx is reset.

SS2TXUF: Master/slave SSI2 TX FIFO Underflow bit. This will be set if there

is attempt to transmit when TX FIFO is empty. This will be cleared
when FIFO gets loaded with data.

CKMODE: This bit reflects the status of the

CLKSEL

(

PE[2]

) input, latched

during

nPOR

. When low, the PLL is running and the chip is

operating in 18.432–73.728 MHz mode. When high the chip is
operating from an external 13 MHz clock.

UBUSY2:

UART2 transmitter busy. This bit is set while UART2 is busy
transmitting data; it is guaranteed to remain set until the complete
byte has been sent, including all stop bits.

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

RSVD

UTXFF2

URXFE2

RSVD

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

RSVD

UBUSY

2

RSVD

CKMOD

E

SS2TXU

F

SS2TXF

F

SS2RXF

E

RESFR

M

RESVAL

SS2RX

OF

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