Cirrus Logic EP73xx - Manual (Page 24)

1-10 EP7309/11/12 User’s Manual - DS508UM4
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Copyright Cirrus Logic, Inc. 2003
Introduction
1
1. All deglitched inputs are via the 16.384 kHz clock. Each deglitched signal must be held active for at least two clock
periods. Therefore, the input signal must be active for at least ~125 µs to be detected cleanly.
The RTC crystal must be populated for the device to function properly.
DAI/CODEC/SSI2 Pin Multiplexing
* p/u = use an ~10 k pull-up
The selection between SSI2 and the CODEC is controlled by the state of the SERSEL
bit in SYSCON2 (See SYSCON2 System Control Register 2). The choice between the
SSI2, CODEC, and the DAI is controlled by the DAISEL bit in SYSCON3 (See
“System
Control Register 3 (SYSCON3)” on page 5-8 ).
Output Bi-Directional Pins
The above output pins are implemented as bi-directional pins to enable the output side of the pad to be monitored and
hence provide more accurate control of timing or duration.
Boundary
Scan
TDI I JTAG data in
TDO O JTAG data out
TMS I JTAG mode select
TCLK I JTAG clock
nTRST I JTAG async reset
Test nTEST[0-1] I
Test mode select inputs. These pins are used in conjunction with the power-on
latched state of nURESET to select between the various device test models.
Oscillators
MOSCIN
MOSCOUT
RTCIN
RTCOUT
I
O
I
O
Main 3.6864 MHz oscillator for 18.432 MHz–90.3168 MHz PLL
Real Time Clock 32.768 kHz oscillator
No Connects N/C No connects should be left as no connects; do not connect to ground
Table 1-5: SSI/CODEC/DAI Pin Multiplexing
SSI2 CODEC DAI Direction Strength
SSICLK PCMCLK SCLK I/O 1
SSITXFR PCMSYNC LRCK I/O 1
SSITXDA PCMOUT SDOUT Output 1
SSIRXDA PCMIN SDIN Input
SSIRXFR p/u* MCLK I/O 1
Table 1-6: Output Bi-Directional Pins
RUN The RUN pin is looped back in to skew the address and data bus from each other.
Drive [0-1]
Drive 0 and 1 are looped back in on power up to determine what polarity the output of the PWM should be when
active.
DD[0-3]
DD[0-3] are looped back on power up to bits 7:4 of the SYSFLG1 register. Pin values are latched upon the enabling of
the LCD Controller via the LCDEN bit. This is useful for reading the panel ID of some LCD modules. When some LCD
modules are reset, they will output a panel ID onto these pins. See the SYSFLG1 register for more information.
Table 1-4: External Signal Functions (Continued)
Function Signal Name Signal Description