Cirrus Logic EP73xx - Manual (Page 12)

EP7309/11/12 User’s Manual - DS508UM4 xi
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Copyright Cirrus Logic, Inc. 2003
List of Tables
Table 1-1: EP73xx Memory Map in External Boot Mode ............................................................................ 1-2
Table 1-2: EP73xx Internal Registers (Little Endian Mode) ........................................................................ 1-4
Table 1-3: EP73xx Internal Registers (Big Endian Mode)............................................................................ 1-6
Table 1-4: External Signal Functions .............................................................................................................. 1-7
Table 1-5: SSI/CODEC/DAI Pin Multiplexing .......................................................................................... 1-10
Table 1-6: Output Bi-Directional Pins .......................................................................................................... 1-10
Table 2-1: Programming Registers ................................................................................................................. 2-1
Table 2-2: ARM720T Core Coprocessor Registers........................................................................................ 2-9
Table 2-3: Status of Peripherals and Clocks by Operating State .............................................................. 2-14
Table 3-1: Timer Registers................................................................................................................................ 3-1
Table 4-1: Interrupt Registers .......................................................................................................................... 4-1
Table 4-2: Vector Addresses by Interrupt Type............................................................................................ 4-3
Table 4-3: Exception Priority Handling ......................................................................................................... 4-4
Table 4-4: Interrupt Allocation in the First Interrupt Register ................................................................... 4-5
Table 4-5: Interrupt Allocation in the Second Interrupt Register .............................................................. 4-5
Table 4-6: Interrupt Allocation in the Third Interrupt Register ................................................................. 4-5
Table 4-7: External Interrupt Sources............................................................................................................. 4-7
Table 5-1: System Registers ............................................................................................................................. 5-2
Table 5-2: Keyboard Column Drive State...................................................................................................... 5-4
Table 5-3: ADC Sample Clock Settings .......................................................................................................... 5-6
Table 5-4: ARM720T Clock Speed Settings ................................................................................................... 5-9
Table 5-5: Default (Power-on Reset) Bus Width Settings .......................................................................... 5-11
Table 6-1: Chip Select Address Ranges for On-Chip Boot ROM ............................................................... 6-2
Table 6-2: Boot Options .................................................................................................................................... 6-2
Table 6-3: Memory Map in External Boot Mode .......................................................................................... 6-3
Table 6-4: Effect of Endianess on Read Operations...................................................................................... 6-4
Table 6-5: Effect on Endianess on Write Operations.................................................................................... 6-4
Table 7-1: SDRAM Registers ........................................................................................................................... 7-1
Table 8-1: SRAM / Expansion Bus Registers ................................................................................................ 8-1
Table 8-2: Bus Width Selection Settings......................................................................................................... 8-3
Table 8-3: Wait States at 13 / 18 MHz Operation......................................................................................... 8-4
Table 8-4: Wait States at 36 MHz Operation ................................................................................................. 8-4
Table 9-1: LCD Registers .................................................................................................................................. 9-1
Table 9-2: Gray Scale Value to Color Mapping ............................................................................................ 9-9
Table 11-1: General Purpose I/O (GPIO) Registers ................................................................................... 11-1
Table 12-1: PWM (Pulse Width Modulator) Registers .............................................................................. 12-2
Table 12-2: PWM Pump Drive Settings ....................................................................................................... 12-3
Table 13-1: LED Flasher Registers ................................................................................................................ 13-1
Table 14-1: Instructions Supported in JTAG Mode.................................................................................... 14-2
Table 14-2: EP73xx Hardware Test Modes.................................................................................................. 14-3
Table 14-3: Oscillator and PLL Test Mode Signals..................................................................................... 14-4
Table 14-4: Software Selectable Test Functionality .................................................................................... 14-4
Table 15-1: SSI Port Registers ........................................................................................................................ 15-1
Table 15-2: ADC Interface Operation Frequencies..................................................................................... 15-3
Table 16-1: DAI/CODEC/SSI2 Registers .................................................................................................... 16-2
Table 16-2: Matrix for Programming the MUX........................................................................................... 16-3
Table 16-3: Pin Sharing for Multiplexor....................................................................................................... 16-4
Table 16-4: Communication Interface Performance................................................................................... 16-4
Table 16-5: Programmable Audio Divisors at 74 MHz ............................................................................. 16-5