Cirrus Logic EP73xx - Manual (Page 120)

15-2 EP7309/11/12 User’s Manual - DS508UM4
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Copyright Cirrus Logic, Inc. 2003
SSI Port
15
CFGBYTE EQU 0x83 ; channel 1 data for ADC data request
TXLENGTH EQU 0x18 ; transmit packet 24 bits (ADC spec0)
TXEN EQU 0x1 ; Transmit enable bit
;
ldr r0, =0x80000000
mov r2, #CFGBYTE
mov r1, #TXLENGTH
mov r3, #TXEN
orr r2,r2,r1, lsl #8
orr r2, r2,r3, lsl #14
str r2, [r0,#0x500] ; Data packet request sent to ADC for channel 1 data
;
again
ldr r1,[r0, #0x140] ; wait loop for SSIBUSY
and r1, #0x4000000
cmp r1, #0x0
bne again
;
ldr r1,[r0, #0x500] ; read first byte of data and discard
str r2, [r0, #0x500] ; request second packet
;
;*****************************************************************************
; wait for SSIBUSY. Insert code required to check SSIBUSY until cleared
;*****************************************************************************
;
ldrb r4,[r0,#0x500]
str r2, [r0, #0x500] ; request third packet
;
;*****************************************************************************
; wait for SSIBUSY. Insert code required to check SSIBUSY until cleared
;*****************************************************************************
;
ldrb r5,[r0,#0x500] ; Actual data stored in r4 and r5
;
Operational Overview
SSI1/ADC Interface
The SSI1 interface has two operating modes. In the default mode, the device is
compatible with the MAXIM MAX148/9 in external clock mode. Similar SPI or
Microwire-compatible devices can be connected directly to the EP73xx.
In the extended mode and with negative-edge triggering selected (the ADCCON and
ADCCKNSEN bits are set, respectively, in the SYSCON3 register), the EP73xx can be