Cirrus Logic EP73xx - Manual (Page 32)

2-6 EP7309/11/12 User’s Manual - DS508UM4

Copyright Cirrus Logic, Inc. 2003
CPU Core
2
Cache is direct-mapped. The copy of the address or data is stored along with an
address tag that is compared with the location in system memory. Cache is also write-
through and uses a replacement algorithm to select which of the four possible
locations will be overwritten in the case of a cache miss.
Write Buffer
The write buffer holds four addresses and eight data words.The MMU defines which
addresses are bufferable. Each address can be associated with any number of data
words. Data words are written to sequential memory starting at that address.
The write buffer becomes full when all four addresses are used or all eight data words
are used. The processor can write into the write buffer at fast cache speed and
continue executing instructions stored in cache while the write buffer stores data to
external memory at the current memory bus speed. If there is a memory fault
generated by a buffered write, the system will not be able to recover from it since the
processor state is not recoverable.
Figure 2-2. ARM720T Cache Organization
e n co d e
D a ta R A M
2 0 4 8 x 3 2 -b it
w o rd
ta g R A M
1 2 8 e n try
ta g R A M
1 2 8 e n try
ta g R A M
1 2 8 en try
ta g R A M
1 2 8 e n try
= ? = ? = ? = ?
3 1 1 1 1 0 4 3 2 1 0
[1:0]
[8:2]
[10:9]
[10:0]
h it d a ta
by te
a d d re sse s
v irtu a l a d d re ss