Cirrus Logic EP73xx - Manual (Page 121)

EP7309/11/12 User’s Manual - DS508UM4 15-3
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Copyright Cirrus Logic, Inc. 2003
SSI Port
1515
15
interfaced to DSP style converters such as the Analog Devices’ AD7811/12 using
nADCCS as a common RFS/TFS line.
Unlike the SSI2/DAI/CODEC interface, SSI1 has a dedicated set of I/O pins and does
not require an elaborate initialization procedure.
The clock output frequency is programmable and only active during data
transmissions to save power. There are four output frequencies selectable, which will
be slightly different depending whether the device is operating in a 13 MHz, 18.432–
73.728 MHz, or 90 MHz mode (see
Table 15-2 ). The required frequency is selected by
programming the corresponding bits 16 and 17 in the System Control Register 1
(SYSCON1) register. The sample clock ( SMPCLK ) always runs at twice the frequency
of the shift clock ( ADCCLK ).
The output channel is fed by an 8-bit shift register when the ADCCON bit of
SYSCON3 is clear. When ADCCON is set, up to 16 bits of configuration command can
be sent, as specified in the SYNCIO register.
The input channel is captured by a 16-bit shift register. The clock and synchronization
pulses are activated by a write to the output shift register. During transfers the
SSIBUSY (synchronous serial interface busy) bit in the system status flags register is
set.
When the transfer is complete and valid data is in the 16-bit read shift register, the
SSEOTI interrupt in asserted and the SSIBUSY bit is cleared. Data can then be read
from this register location. The interrupt is cleared on the data is read from the
SYNCIO register. SSEOTI is unmasked in the INTMR1 register and the status is read
in the INTSR1 register.
An additional sample clock ( SMPCLK ) can be enabled independently and is set at
twice the transfer clock frequency.
This interface has no local buffering capability and is only intended to be used with
low bandwidth interfaces, such as an ADC for a touch screen interface.
Table 15-2: ADC Interface Operation Frequencies
SYSCON1
bit 17
SYSCON1
bit 16
13.0 MHz Operation
ADCCLK Frequency
(kHz)
18.432–73.728 MHz
Operation ADCCLK
Frequency (kHz)
90.3168 MHz
Operation ADCCLK
Frequency (kHz)
0 0 4.2 4 4.9
0 1 16.9 16 19.6
1 0 67.7 64 78.4
1 1 135.4 128 156.8