Debug interface, Cpu register definitions, Debug interface -7 – Cirrus Logic EP73xx User Manual
Page 33: Cpu register definitions -7
EP7309/11/12 User’s Manual - DS508UM4
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Copyright Cirrus Logic, Inc. 2003
CPU Core
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Debug Interface
JTAG (Joint Test Action Group) or IEEE 1149 provides a boundary scan test interface
with 5 dedicated signals connected directory to the CPU core:
• TRST - Test Reset (active low)
• TCK - Test Clock
• TMS - Test Mode Select
• TDI - Test Data In
• TDO - Test Data Out
See
for more information on debugging the EP73xx via the JTAG interface.
CPU Register Definitions
ARM has 37 32-bit internal registers. If operating in Thumb mode, the processor must
switch to ARM mode before taking an exception. The return instruction will restore
the processor to Thumb state. Most tasks are executed out of User mode.
User:
Unprivileged normal operating mode.
FIQ:
Fast interrupt (high priority) mode when FIQ is asserted
IRQ:
Interrupt request (normal) mode when IRQ is asserted
Supervisor:
Software interrupt instruction (SWI) or reset will cause entry into
this mode
Abort:
Memory access violation will cause entry into this mode
Undef:
Undefined instructions
System:
Privileged mode. Uses same registers as user mode
illustrates the use of all registers for the following core
operating modes. Each will bank or store a specific number of registers. Banked
register information is not shared between modes. FIQs bank the fewest number of
registers which increases performance.