Cirrus Logic EP73xx - Manual (Page 92)

9-2 EP7309/11/12 User’s Manual - DS508UM4
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Copyright Cirrus Logic, Inc. 2003
LCD Interface
9
Programming Example
;************************************************************************
; LCD Controller Configuration for a 640x240x4 bpp LCD Panel (ALPS)
; AC Prescale = 0x18 (LCD Manufacturer Number)
; Refresh Rate = 60 Hz
; LCD Palettes require 1 to 1 mapping between pixel value to intensity
; Pixel Prescale = 3
;************************************************************************
;
LCDCON EQU 0xF01CF2BF ; Value for LCDCON register for above req.
PALLSW EQU 0x76543210 ; 1-1 mapping for least sig. palette reg.
PALMSW EQU 0xFECDBA98 ; 1-1 mapping for most sig. palette reg.
LCDFRAME EQU 0xC ; LCD Frame Buffer Start Location (physical)
ldr r1, =LCDCON
str r1, [r12, #0x02C0] ; store to LCDCON at 0x8000.02C0
ldr r1, =PALLSW
str r1, [r12, #0x0580] ; store to PALLSW at 0x8000.0580
ldr r1, =PALMSW
str r1, [r12, #0x0540] ; store to PALMSW at 0x8000.0540
ldr r1, =LCDFRAME
mov r1,r1, lsl #28 ; 0xC in upper 8 bits
ldr r11, =0x80001000
str r1, [r11, #0x0] ; OxC for location 0xC0000000(SDRAM)
;*****************************************************************************
; Configuration Complete. LCD Controller can now be turned on
;*****************************************************************************
;
ldr r1, =0x1000 ; Enable LCDEN bit
ldr r0, [r12, #0x100] ; Load value from SYSCON1
orr r0,r0,r1
str r0, [r12, #0x100] ; LCDEN bit set in SYSCON1
;
Operational Overview
LCD Controller External Memory
The LCD frame buffer is mapped to any external SRAM or SDRAM by means of the
frame buffer start address registers FBADDR. The eight bit value stored in the register
represents the physical location of this memory region (before the MMU is turned
on), not the virtual memory region. This memory must be controlled by one of the
processor chip selects.