Cirrus Logic EP73xx - Manual (Page 143)

EP7309/11/12 User’s Manual - DS508UM4 16-19
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Copyright Cirrus Logic, Inc. 2003
DAI/CODEC/SSI2
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down to the bottom, the Right Channel Transmit logic uses the new value within the
FIFO for transmission. When the RCTU bit is set, an interrupt request is made.
RCRO:
The Right Channel Receive FIFO Overrun Status Bit (RCRO) is set when the right
channel receive logic attempts to place data into the Right Channel Receive FIFO after
it has been completely filled. Each time a new piece of data is received, the set signal
to the RCRO status bit is asserted, and the newly received data is discarded. This
process is repeated for each new sample received until at least one empty FIFO entry
exists. When the RCRO bit is set, an interrupt request is made.
LCTU:
The Left Channel Transmit FIFO Underrun Status Bit (LCTU) is set when the Left
Channel Transmit logic attempts to fetch data from the FIFO after it has been
completely emptied. When an underrun occurs, the Left Channel Transmit logic
continuously transmits the last valid left channel value which was transmitted before
the underrun occurred. Once data is placed in the FIFO and it is transferred down to
the bottom, the Left Channel Transmit logic uses the new value within the FIFO for
transmission. When the LCTU bit is set, an interrupt request is made.
LCRO:
The Left Channel Receive FIFO Overrun Status Bit (LCRO) is set when the Left
Channel Receive logic places data into the Left Channel Receive FIFO after it has been
completely filled. Each time a new piece of data is received, the set signal to the LCRO
status bit is asserted, and the newly received sample is discarded. This process is
repeated for each new piece of data received until at least one empty FIFO entry
exists. When the LCRO bit is set, an interrupt request is made.
RCNF:
The Right Channel Transmit FIFO Not Full Flag (RCNF) is a read-only bit which is set
whenever the Right Channel Transmit FIFO contains one or more entries which do
not contain valid data and is cleared when the FIFO is completely full. This bit can be
polled when using programmed I/O to fill the Right Channel Transmit FIFO. This bit
does not request an interrupt.
LCNF:
The Left Channel Transmit FIFO Not Full Flag (LCNF) is a read-only bit which is set
when ever the Left Channel Transmit FIFO contains one or more entries which do not
contain valid data. It is cleared when the FIFO is completely full. This bit can be
polled when using programmed I/O to fill the Left Channel Transmit FIFO. This bit
does not request an interrupt.
LCNE:
The Left Channel Receive FIFO Not Empty Flag (LCNE) is a read-only bit which is set
when ever the Left Channel Receive FIFO contains one or more entries of valid data
and is cleared when it no longer contains any valid data. This bit can be polled when
using programmed I/O to remove remaining data from the receive FIFO. This bit
does not request an interrupt.