Programming example, Pll multiplier write register (pllw), Pll multiplier read register (pllr) – Cirrus Logic EP73xx User Manual

Page 37: External 13mhz clock

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EP7309/11/12 User’s Manual - DS508UM4

2-11

Copyright Cirrus Logic, Inc. 2003

CPU Core

22

2

internal PLL clock so adjustments and consideration will need to be taken into
account.

PLL Equation: (PLL Multiplier/2)* 3.686 MHz = PLL Frequency

ex. For 90 MHz operation, PLL Multiplier = 49

It should be noted that using the PLL Multiplier to achieve 90 MHz operation will
result in a shifting up of frequencies and rates derived from the PLL by 22.5%. For
example, the data bus will move from 36 MHz to 45 MHz. Take care when using a
PLL-derived system because such shifting may be in effect.

Programming Example

;********************************************************************************

; Sample code for entering the proper value into the PLL Multiplier Write Register
to

; achieve 90 MHz operation. This is done after setting the PLL to 74 MHz in

; SYSCON3.

;********************************************************************************

;begin

PLL_Multiplier_Write_Register EQU 0x80002610; the location of the PLL multiplier

;Write register

Value_For_90_MHz_Operation EQU 0x31000000

; the value for 90Mhz operation

ldr r0= PLL_Multiplier_Write_Register

ldr r1= Value_For_90_MHz_Operation

str r1, [r0]

; store R1 at R0

; end

PLL Register Descriptions

PLL Multiplier Write Register (PLLW)

Address:

0x8000.2610, Write Only

Definition:

PLL Multiplier is written to the upper 8 bits of this register only. Do
not read from this location

PLL Multiplier Read Register (PLLR)

Address:

0x8000.A5A8, Read Only

Definition:

PLL Multiplier value written to above register can be read at this
location in the upper 8 bit only. Do not write to this location.

Note: Increasing the PLL clock too high will cause the processor to abort any

operation. Decreasing the speed will not clear the condition. A system reset and
a lower setting will be required. PLL must be preset to 74MHz via SYSCON3
before PLL multiplier can be used properly.

External 13 MHz Clock

An external 13 MHz crystal oscillator can be used to drive the EP73xx. When selected,
the CPU and external buses are both clocked at 13 MHz. In this configuration, the

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