Cirrus Logic EP73xx - Manual (Page 93)

EP7309/11/12 User’s Manual - DS508UM4 9-3

Copyright Cirrus Logic, Inc. 2003
LCD Interface
99
9
The frame buffer start address begins with 0x0000000 within each memory region to
the value programmed with the FBADDR will define only the most significant byte of
the start address. For instance, programming the register with 0xC will define the
frame buffer start address to be 0xC0000000. The register can therefore be
programmed with values from 0x1 to 0xC, depending on the external RAM/SDRAM
memory location. Values 0x7 and 0x8 are dedicated system memory for the processor
Boot ROM and internal registers respectively so these values are not valid for the
LCD frame buffer. This region cannot be used. If internal SRAM is used (FBADDR =
0x6), the amount of storage is limited to 48 Kbytes but is accessible. Calculating total
memory requirements will be necessary prior to using this fixed memory region.
The screen is mapped as on contiguous block of memory where each horizontal line
of pixels is mapped to a set of consecutive bytes or words. Pixel 0 represent the LSB in
a word wide access of the frame buffer memory consistent with little endian
configuration.
LCD DMA Controller
The DMA controller for the LCD controller is dedicated to the controller and is
designed to fetch from the frame buffer memory and fill a nine-word deep FIFO.
Once the controller is enabled, it will continue to operate without requiring service
from the CPU. The DMA controller will request data when there are only 5 words
remaining in the FIFO. The DMA bandwidth can be calculated based on the following
criteria:
• refresh rate
• panel size
• bits per pixel
1/2 VGA with 4 bpp@ 80 Hz refresh = (640x240) x 4 bps x 80 Hz = 6.14 Mbytes/s.
This assumes that the frame buffer is stored in a 32-bit-wide memory. Sixteen-bit-
wide memory can be used which will double the access time and the DMA latency
DMA latency calculations are based on a 32-bit-wide memory. Assuming 1/2 VGA, 5
words for a FIFO fill, 80 Hz refresh rate at 4 bpp, the maximum allowable latency can
only be approximately:
(5 words x 32 bits/word)/(640x240x4 bppx80 Hz) = 3.25
µs.
This number represents the worst case latency or the total number of cycles from
when the DMA request appears to when the first DMA data word actually becomes
available or is written to the FIFO. DMA has the highest priority in the system so the
FIFO fill will always occur next in sequence.
The maximum number of cycles between a DMA request for data and the first word
seen in the FIFO is 42. At 13 MHz bus speed (77 ns cycle time), the latency is
approximately 3.23us. At 18 MHz, the latency is reduced to 2.26
µs. At 36 MHz bus
speed, or 74 MHz internal CPU speed, the number is even further reduce to about
1.49
µs. The calculation is more complex. The total number of cycles at 36 MHz is
(12x4) + 7 = 55.