Cirrus Logic EP73xx - Manual (Page 86)

8-2 EP7309/11/12 User’s Manual - DS508UM4

Copyright Cirrus Logic, Inc. 2003
SRAM/Expansion Bus Controller
8
MemConfig1value EQU 0x3c011814 ; CS0-CS3 configuration values
MemConfig2value EQU 0x0000001e ; CS6(Internal SRAM) CS7(Internal Boot ROM)
;*****************************************************************************
; configure nCS0 - nCS3
;*****************************************************************************
;
ldr r1, =MemConfig1value
str r1,[r12,#0x0180] ; MEMCFG1 = 0x8000.0180
;
;*****************************************************************************
; configure nCS4 - nCS5
;*****************************************************************************
;
ldr r1, =MemConfig2value
str r1,[r12,#0x01c0] ; MEMCFG2 = 0x8000.01c0
;
Operational Overview
All chip selects can be configured as 8, 16, or 32-bit wide memory to interface to a
wide range of external hardware. Each chip select has a default address at power on
reset, but can change based on how the pagetable in the MMU remaps the memory.
At power on reset, the initial setting for the Bus width for all chip selects will depend
on the state of
PE1 and PE0 at that time. The software can then reconfigure the chip
selects. Wait states are programmable from 1-8 additional clocks.
There are two internal registers for programming the chip selects: MEMCFG1 and
MEMCFG2. These registers are described below.
Note: At power-on-reset or system reset, all values are cleared.
There are a total of six chip selects CS0 - CS5 , that are user controlled to access memory
or devices throughout the system. Programming includes, bus width from 8-32 bits,
wait states, and bus clock access, in the event that the interface is not asynchronous.
Note: The memory area decode by CS[6] is reserved for on-chip SRAM and does not require
programming. The default configuration is 32-bit wide and no wait states.CS[7] accesses internal boot
ROM and defaults to 8-bit wide and no wait states. No additional programming is possible.