Cirrus Logic EP73xx - Manual (Page 142)

16-18 EP7309/11/12 User’s Manual - DS508UM4
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Copyright Cirrus Logic, Inc. 2003
DAI/CODEC/SSI2
16
Full Bit Descriptions
RCTS:
The Right Channel Transmit FIFO Service Request Flag (RCTS) is a read-only bit
which is set when the Right Channel Transmit FIFO is nearly empty and requires
service to prevent an underrun. RCTS is set any time the Right Channel Transmit
FIFO has four or fewer entries of valid data (half full or less), and is cleared when it
has five or more entries of valid data. When the RCTS bit is set, an interrupt request is
made unless the Right Channel Transmit FIFO interrupt request mask (RCTM) bit is
cleared. After the CPU fills the FIFO such that four or more locations are filled within
the Right Channel Transmit FIFO, the RCTS flag (and the service request and/or
interrupt) is automatically cleared.
RCRS:
The Right Channel Receive FIFO Service Request Flag (RCRS) is a read-only bit which
is set when the Right Channel Receive FIFO is nearly filled and requires service to
prevent an overrun. RCRS is set any time the Right Channel Receive FIFO has six or
more entries of valid data (half full or more), and cleared when it has five or fewer
(less than half full) entries of data. When the RCRS bit is set, an interrupt request is
made unless the Right Channel Receive FIFO interrupt request mask (RCRM) bit is
cleared. After six or more entries are removed from the receive FIFO, the LCRS flag
(and the service request and/or interrupt) is automatically cleared.
LCTS:
The Left Channel Transmit FIFO Service Request Flag (LCTS) is a read-only bit which
is set when the Left Channel Transmit FIFO is nearly empty and requires service to
prevent an underrun. LCTS is set any time the Left Channel Transmit FIFO has four
or fewer entries of valid data (half full or less). It is cleared when it has five or more
entries of valid data. When the LCTS bit is set, an interrupt request is made unless the
Left Channel Transmit FIFO interrupt request mask (LCTM) bit is cleared. After the
CPU fills the FIFO such that four or more locations are filled within the Left Channel
Transmit FIFO, the LCTS flag (and the service request and/or interrupt) is
automatically cleared.
LCRS:
The Left Channel Receive FIFO Service Request Flag (LCRS) is a read-only bit which
is set when the Left Channel Receive FIFO is nearly filled and requires service to
prevent an overrun. LCRS is set any time the Left Channel Receive FIFO has six or
more entries of valid data (half full or more), and cleared when it has five or fewer
(less than half full) entries of data. When the LCRS bit is set, an interrupt request is
made unless the Left Channel Receive FIFO interrupt request mask (LCRM) bit is
cleared. After six or more entries are removed from the receive FIFO, the LCRS flag
(and the service request and/or interrupt) is automatically cleared.
RCTU:
The Right Channel Transmit FIFO Underrun Status Bit (RCTU) is set when the Right
Channel Transmit logic attempts to fetch data from the FIFO after it has been
completely emptied. When an underrun occurs, the Right Channel Transmit logic
continuously transmits the last valid right channel value which was transmitted
before the underrun occurred. Once data is placed in the FIFO and it is transferred