Cirrus Logic EP73xx - Manual (Page 36)

2-10 EP7309/11/12 User’s Manual - DS508UM4
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Copyright Cirrus Logic, Inc. 2003
CPU Core
2
• Start-up resistor is not necessary. One is provided internally.
• Start-up capacitors may be placed on each side of the external crystal and
ground. Value for each should be around 10 pF but also should be selected
based upon crystal specifications. Capacitance of the traces and crystal
leads should be subtracted from the load capacitor value for precision.
• The crystal should have a maximum of 5 ppm frequency drift over the
chips’s operating temperature range.
• Voltage for the crystal must be 2.5 V+ 0.2 V.
A digital clock source can be used to drive the RTCIN on the EP73xx. Voltage levels of
the clock should match that of Vdd supply for the processor pads or the supply
voltage used to drive the non-core Vdd pins on the EP73xx. In this configuration, the
output clock pin should be left floating.
On-Chip PLL
The on-chip PLL is generated from an external 3.686 MHz crystal. The ARM720T
CPU clock, from the PLL, can then be programmed to 18.432, 36.864, 49.152, 73.728,
and 90.3168 MHz.
The external bus is controlled by the PLL and defaults to 18 MHz until the internal
CPU clock reaches 36 MHz or above, at which point the external bus runs at 1/2 the
CPU clock speed. Modifying the PLL speed in the SYSCON3 register will require a
NOP at the next instruction for the system to stabilize. Internally, the state controller
switches from the current clock to the new clock speed, by bringing both clocks low,
then perform the switch to the new speed to insure a glitch-free transition.
PLL Clock Characteristics and Interface Requirements
• The 3.6864 MHz frequency should be created by the crystals fundamental
tone.
• Start-up resistor is provided internally
• Value of loading capacitors should be in the range of 10 pF. However, the
actual value will depend on the crystal’s specifications. The total sum of the
capacitance on the pins and the leads should factor into the value of the
loading capacitors.
• The crystal should have a maximum of 10 ppm frequency drift over the
operating temperature of the chip.
A digital clock source can be used to drive the MOSCIN pin of the EP73xx. Voltage
levels of the clock source should match the Vdd supply for the EP73xx non-core pins.
The output clock pin (
MOSCOUT ) should be left floating.
PLL Multiplier for 90 MHz Operation
There are two internal register that can be used to increase the PLL frequency beyond
74 MHz. The intention is to increase the speed to 90 MHz for use with the DAI and to
increase overall performance. This can affect devices and their times running from the