Rockwell Automation D64046.5.1 U MNL WIN DDMC - Manual (Page 151)

Reference Information
Appendix A
A-7
The control status bits are:
15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
EN ES ER ST ME TE RS DV PC MR TB
The following table defines the control/status bits
Bit: Definition:
EN Rung Enable
ES Error Step indicator; if true, sequencer is in an error step
ER Error; true if runtime error detected
ST Step Transition; true for one PLC scan if step transition
occurred
ME Message Enable; true if message is to be sent
TE Timer Enable; true if timer is used in current step
RS Reset Sequencer; a status bit; if true, sequencer is in normal
run mode; if false, sequencer is in step zero mode.
DV Future use
PC Precheck; if 0, precheck is enabled and the SDS, at state
transition, will check if the destination step expected inputs
match the mapped inputs; if 1, precheck is disabled and the
SDS instruction, at state transition, will not check the
destination step expected inputs
MR Mismatch Reset; a control bit; if the SDS instruction is in a
mismatch condition, setting this bit to 1 will release the
mismatch check and the SDS instruction will start from step 0
to find a step to enter
TB Time base; the instruction entry allows the programmer to
select either .01 or 1.0 second time base for the timer
You can obtain information about the control file from the Extended Status
screen in the SDS instruction. The Extended Status screen provides the
status of specific bits in the control file in user-friendly terms.
Read this section to learn about reference information for the DFA
instruction.
Execution Times
Tables A.I and A.J show the execution times per program scan for a DFA
instruction in the PLC-5 or the PLC-5/250 with 8, 16, and 32 I/O.
Reference Information for
the DFA Instruction