16 process data interface (pdi), 1 pdi selection and configuration, Process data interface (pdi) – BECKHOFF EtherCAT Technology Section I User Manual
Page 111: Pdi selection and configuration, Table 57: available pdis depending on esc
Process Data Interface (PDI)
Slave Controller
– Technology
I-91
16 Process Data Interface (PDI)
The Process Data Interface (PDI) realizes the connection between slave application and ESC. Several
types of PDIs are defined, e.g., serial and parallel µController interfaces and Digital I/O interfaces.
Table 57 gives an overview of the available PDI types for each ESC.
Due to the high dependency between EtherCAT and PDI accesses to memory, registers, and
especially SyncManagers, the internal PDI interface can achieve a maximum throughput of approx.
12.5 Mbyte/s.
Details on individual PDI functionality can be found in Section III of the Hardware Data Sheet for a
specific ESC.
Table 57: Available PDIs depending on ESC
PDI number
(PDI Control
register
0x0140)
PDI name
E
S
C
20
IP
Co
re
E
T
11
00
E
T
12
00
0
Interface deactivated
x
x
x
x
4
Digital I/O
x
x
x
5
SPI Slave
x
x
x
x
7
EtherCAT Bridge (port 3)
x
8
16 Bit async. µC
x
x
x
9
8 Bit async. µC
x
x
x
10
16 Bit sync. µC
x
11
8 Bit sync. µC
x
16
32 Digital Input/0 Digital Output
x
17
24 Digital Input/8 Digital Output
x
18
16 Digital Input/16 Digital Output
x
19
8 Digital Input/24 Digital Output
x
20
0 Digital Input/32 Digital Output
x
128
On-chip bus
x
Others
Reserved
NOTE: On-Chip bus: different On-chip buses are supported by the EtherCAT IP Core for Altera FPGAs and the
EtherCAT IP Core for Xilinx FPGAs.
16.1 PDI Selection and Configuration
Typically, the PDI selection and configuration is part of the ESC Configuration Area of the SII
EEPROM.
Some ESCs (e.g. IP Core) have the PDI selected and configured at power-on time. In this case, the
ESC Configuration Area should reflect the actual settings, although they are not evaluated by the ESC
itself.
For the other ESCs, the PDI becomes active after the SII EEPROM is successfully loaded. All PDI
pins are inactive (high impedance) until then (as well as the DC Sync/Latch signals). Some ESCs and
PDIs provide an EEPROM_Loaded signal, which indicates that the EEPROM is successfully loaded
and the PDI can be used. Attach a pull-down resistor to the EEPROM_Loaded pin, because it is also
not driven (high impedance) until the EEPROM is successfully loaded. The PDI of an IP Core is active
after reset is released, which enables e.g. EEPROM emulation by a µController.
Take care of Digital Output signals and DC SyncSignals while the EEPROM is not loaded to achieve
proper output behavior.