BECKHOFF EtherCAT Technology Section I - Manual (Page 38)

Physical Layer Common Features
I-18 Slave Controller – Technology
4.2 Selecting Standard/Enhanced Link Detection
Some ESCs distinguish between standard and enhanced link detection. Enhanced link detection
provides additional security mechanisms regarding link establishment and surveillance. Using
enhanced link detection is recommended for Ethernet PHY ports (refer to chapter 6.5 for compatibility
issues with EBUS enhanced link detection). Some ESCs only support global Enhanced Link Detection
configuration for all ports, some support port-wise configuration.
After power-on, enhanced link detection is enabled by default. It is disabled or remains enabled after
the SII EEPROM is loaded according to the EEPROM setting (register 0x0141). An invalid EEPROM
content will also disable enhanced link detection.
The EEPROM setting for enhanced Link detection is only taken over at the first EEPROM loading after
power-on or reset. Changing the EEPROM and manually reloading it will not affect the enhanced link
detection enable status (register 0x0110[2]), even if the EEPROM could not be read initially.
Registers used for Enhanced link detection are listed in Table 11.
Table 11: Registers for Enhanced Link Detection
Register Address Name Description
0x0141[1] ESC Configuration Enable/disable Enhanced link detection for all
ports
0x0141[7:4] ESC Configuration Enable/disable Enhanced link detection port-
wise
0x0110[2] ESC DL Status Enhanced link detection status
NOTE: Some of these register bits are set via SII EEPROM/IP Core configuration. Some of the registers are not
available in specific ESCs. Refer to Section II and III for details.