BECKHOFF EtherCAT Technology Section I - Manual (Page 48)

Ethernet Physical Layer
I-28 Slave Controller – Technology
5.10.2 Logical Interface
The MI of the ESC is typically controlled by EtherCAT via the MI registers 1 .
Table 17: MII Management Interface Register Overview
Register Address Description
0x0510:0x0511 MII Management Control/Status
0x0512 PHY Address
0x0513 PHY Register Address
0x0514:0x0515 PHY Data
The MI supports two commands: write to one PHY register or read one PHY register.
5.10.2.1 MI read/write example
The following steps have to be performed for a PHY register access:
1. Check if the Busy bit of the MI Status register is cleared and the MI is not busy.
2. Write PHY address to PHY Address register.
3. Write PHY register number to be accessed into PHY Register Address register (0-31).
4. Write command only: put write data into PHY Data register (1 word/2 byte).
5. Issue command by writing to Control register.
For read commands, write 1 into Command Register Read 0x0510[8].
For write commands, write 1 into Write Enable bit 0x0510[0] and also 1 into Command Register
Write 0x0510[9]. Both bits have to be written in one frame. The Write enable bit realizes a write
protection mechanism. It is valid for subsequent MI commands issued in the same frame and self-
clearing afterwards.
6. The command is executed after the EOF, if the EtherCAT frame had no errors.
7. Wait until the Busy bit of the MI Status register is cleared.
8. Check the Error bits of the MI Status register. The command error bit is cleared with a valid
command or by clearing the command register. The read error bit indicates a read error, e.g., a
wrong PHY address. It is cleared by writing to the register.
9. Read command only: Read data is available in PHY Data register.
NOTE: The Command register bits are self-clearing. Manually clearing the command register will also clear the
status information.
5.10.2.2 MI Interface Assignment to ECAT/PDI
The EtherCAT master controls the MI Interface (default) if the MII Management PDI Access State
register 0x0517[0] is not set. The EtherCAT master can prevent PDI control over the MI Interface, and
it can force the PDI to release the MI Interface control. After power-on, the PDI can take over MI
Interface control without any master transactions.
1 ET1100 only: MI Control is transferred to PDI if the Transparent Mode is enabled. IP Core: MI Control by PDI is
possible.