BECKHOFF EtherCAT Technology Section I - Manual (Page 84)

Distributed Clocks
I-64 Slave Controller – Technology
9.2.3.6 SyncSignal Initialization Example
The SyncSignal generation is initialized with the following procedure:
1. Enable DC SYNC Out Unit in ESC Configuration register (0x0141[2]=1; specific ESCs only)
2. Set SYNC/Latch PDI Configuration register (0x0151, initialized by SII EEPROM) to SYNC0/1
output with appropriate driver settings.
3. Set Pulse Length register (0x0982:0x0983, initialized by EEPROM) to pulse length of SYNC
signals. Select a value > 0 ns for cyclic repetition of the SyncSignals
4. Assign Sync Unit to ECAT or PDI (0x0980, part of ESI)
5. Set cycle time of SYNC0 signal (0x09A0:0x09A3) and for SYNC1 signal (0x09A4:0x09A7)
6. Set Start Time of Cyclic Operation (0x0990:0x0997) to a time later than the time the cyclic
generation will be activated (end of activation frame; e.g., read the System Time and add the time
for writing Start Time and Activation). For 32 bit DCs, the SyncSignal generation will start at worst
after a turn-over of the System Time (~ 4 s), but with 64 bit DCs, SyncSignal generation may start
in hundreds of years.
7. Activate Cyclic Operation (0x0981[0]=1) to start cyclic generation of SyncSignals and activate
SYNC0/1 generation (0x0981[2:1]=0x3). The Sync Unit waits until the Start Time of Cyclic
Operation is reached for the generation of the first SYNC0 pulse.
Register Start Time of Cyclic Operation and register Next SYNC1 pulse can be read to get the time of
the next output event. In the acknowledged modes, the Sync0/1 Status registers (0x098E:0x098F)
give the status of the SyncSignals. The SyncSignals are acknowledged by reading the SYNC0/1
Status registers.
9.2.4 LatchSignals
The DC Latch Unit enables time stamping of LatchSignal events for two external signals, LATCH0 and
LATCH1. Both rising edge and falling edge time stamps are recorded. Additionally, time stamping of
SyncManager events is possible with some ESCs.
LatchSignals are sampled with a sample rate of 100 MHz, the corresponding time stamp has an
internal jitter of 11 ns.
The state of the LatchSignals can be read from the Latch Status registers (0x09AE:0x09AF) – if
supported by the ESC.
The DC Latch Unit supports two modes: single event or continuous mode, configured in the Latch0/1
Control registers (0x09A8:0x09A8).