BECKHOFF EtherCAT Technology Section I - Manual (Page 97)

SII EEPROM
Slave Controller – Technology I-77
11.2.3 Read/Write/Reload Example
The following steps have to be performed for an SII EEPROM read or write access:
1. Check if the Busy bit of the EEPROM Status register is cleared (0x0502[15]=0) and the EEPROM
interface is not busy, otherwise wait until the EEPROM interface is not busy anymore.
2. Check if the Error bits of the EEPROM Status register are c leared. If not, write “000” to the
command register (register 0x0502 bits [10:8]).
3. Write EEPROM word address to EEPROM Address register.
4. Write command only: put write data into EEPROM Data register (1 word/2 byte only).
5. Issue command by writing to Control register.
a) For a read command, write 001 into Command Register 0x0502[10:8].
b) For a write command, write 1 into Write Enable bit 0x0502[0] and 010 into Command Register
0x0502[10:8]. Both bits have to be written in one frame. The Write enable bit realizes a write
protection mechanism. It is valid for subsequent EEPROM commands issued in the same frame
and self-clearing afterwards. The Write enable bit needs not to be written from PDI if it controls the
EEPROM interface.
c) For a reload command, write 100 into Command Register 0x0502[10:8].
6. The command is executed after the EOF if the EtherCAT frame had no errors. With PDI control,
the command is executed immediately.
7. Wait until the Busy bit of the EEPROM Status register is cleared.
8. Check the Error bits of the EEPROM Status register. The Error bits are cleared by clearing the
command register. Retry command (back to step 5) if EEPROM acknowledge was missing. If
necessary, wait some time before retrying to allow slow EEPROMs to store the data internally.
9. a) For a Read command: Read data is available in EEPROM Data registers (2 or 4 Words,
depending on ESC – check register 0x0502[6]).
b) For a Reload command: ESC configuration is reloaded into appropriate registers.
NOTE: The Command register bits are self-clearing. Manually clearing the command register will also clear the
status information.
11.2.4 EEPROM Emulation
The EEPROM emulation mode is used in ESCs with a non-volatile memory (NVRAM) attached to a
µController. The ESC configuration and the device description can be stored in the NVRAM of the
µController, e.g., together with the program or FPGA configuration code. An additional I²C EEPROM
chip for the ESC is not needed anymore if EEPROM emulation is used.
The µController emulates the EEPROM interface actions of the ESC and executes all EEPROM
reload, read, and write requests. EEPROM write data is stored in the NVRAM of the µController, and
EEPROM read data is read from the NVRAM and presented to the EEPROM interface of the ESC.
From the EtherCAT master’s point of view, EEPROM emulation mode is equivalent to an I²C
EEPROM. The master issues EEPROM commands and waits until the EEPROM interface is not busy
anymore.
In EEPROM emulation mode, the EEPROM interface of the ESC issues an interrupt to the µController
if an EEPROM command is pending and sets the busy bit. While the busy bit is set, the µController
can read out the command and the EEPROM address. For a write access, write data is present in the
data register. For a read command, read data has to be stored in the data register by the µController.
A reload command requires the µController to place specific reload data in the data register, refer to
section II for details.
Once the µController has finished reading/writing the EEPROM data register, it acknowledges the
command by writing to the EEPROM command register bits. The µController has to write the
command value it has executed into the EEPROM command register. Errors can be indicated using
two of the error bits. After acknowledging the command, the EEPROM state machine is not busy
anymore and the interrupt is released.
NOTE: The EEPROM can be assigned to the PDI even if EEPROM Emulation is used.