BECKHOFF EtherCAT Technology Section I - Manual (Page 96)

SII EEPROM
I-76 Slave Controller – Technology
11.2.1.1 Missing Acknowledge
Missing acknowledges from the EEPROM chip are a common issue, especially if a fast PDI uses the
EEPROM interface. E.g., a write access to the EEPROM with missing acknowledge may look like this:
1. ECAT/PDI issue write command (first command)
2. ESC is busy transferring the write data to the EEPROM chip.
3. ESC is not busy anymore. EEPROM chip is internally busy transferring data from input buffer to
storage area.
4. ECAT/PDI issue a second command.
5. ESC is busy transferring the write data to the EEPROM chip. EEPROM chip does not
acknowledge any access until internal transfer has finished (may take up to several ms).
6. ESC is not busy anymore. Error Acknowledge/Command bit is set. (ESC has to re-issue the
second command after EEPROM chip is finished and the command is acknowledged).
7. EEPROM chip finishes internal transfer.
8. ESC re-issues the second command, the command is acknowledged and executed successful.
This is also possible for a read access, because some EEPROM chips require an idle period between
any two accesses. During this idle period, they do not acknowledge any access.
11.2.2 SII EEPROM Interface Assignment to ECAT/PDI
The EtherCAT master controls the EEPROM interface (default) if EEPROM configuration register
0x0500[0]=0 and EEPROM PDI Access register 0x0501[0]=0, otherwise PDI controls the EEPROM
interface. These access rights should be checked by both sides before using the EEPROM Interface.
A typical EEPROM interface control hand-over is as follows:
1. ECAT assigns EEPROM interface to PDI by writing 0x0500[0]=1
2. If PDI wishes to access EEPROM, it takes over EEPROM control by writing 0x0501[0]=1.
3. PDI issues EEPROM commands.
4. After PDI has finished EEPROM commands, PDI releases EEPROM control by writing
0x0501[0]=0.
5. ECAT may take back the EEPROM interface by writing 0x0500[0]=0
6. ECAT checks EEPROM control by reading 0x0501
7. ECAT issues EEPROM commands.
If the PDI does not release EEPROM control (e.g. because of a software failure), ECAT can force
releasing the access:
1. ECAT writes 0x02 to register 0x0500 (as the result, 0x0501[0] is cleared)
2. ECAT writes 0x00 to register 0x0500
3. ECAT has control over EEPROM interface