BECKHOFF EtherCAT Technology Section I - Manual (Page 99)

SII EEPROM
Slave Controller – Technology I-79
11.3.3 I²C Access Protocol
Each EEPROM access begins with a Start condition and ends with a Stop condition. Data is
transferred byte-wise, and each byte is acknowledged by the recipient.
The Start condition is a falling edge on EEPROM_DATA while EEPROM_CLK is high, the Stop
condition is a rising edge on EEPROM_DATA while EEPROM_CLK is high. In all other cases,
EEPROM_DATA has to remain stable while EEPROM_CLK is high, as this indicates valid data. A byte
transfer is acknowledged in an additional bit, which is driven low by the recipient of the byte transfer if
it acknowledges the byte.
NOTE: If the EEPROM does not acknowledge an access (Ack bit=high), it might be busy internally.
Especially if the EERPOM interface is handled by a µController via the PDI, this situation may come
up, because many µControllers can write to the EEPROM interface much faster than many EEPROMs
can transfer the data from their input registers into their NVRAM.
The first byte of an I²C access is the Control Byte (Bit 7/MSB is transferred first):
Table 43: I²C Control Byte
Bit Description
0 Read/Write access:
0:
Write
1: Read
[3:1] Chip Select Bits/Highest Address Bits
[7:4] Control Code: 1010
Depending on the access, either read data will follow or additional address bytes and write data. This
is described in the following chapters.
The EEPROM has an internal byte pointer, which is incremented automatically after each data byte
transfer.
For more details about the I²C protocol, refer to “The I²C-Bus Specification”, available from NXP
(
http://www.nxp.com , document number 39340011) and http://www.i2c-bus.org .
11.3.3.1 Write Access
An EEPROM write access always writes one word (2 bytes) to the EEPROM. In this case, page
boundaries are not relevant, because they will not be violated.
The ESC will perform the following steps for a write access to the EERPOM:
Table 44: I²C Write Access
Step Description Up to 16 Kbit 32 Kbit – 4 Mbit
1 Start condition
2 Control Byte (Write) A[10:8] A[18:16]
3* High Address Byte Not preset A[15:8]
4 Low Address Byte A[7:0] A[7:0]
5 Low Data Byte D[7:0]
7 High Data Byte D[15:8]
8 Stop condition
* This step is only for EEPROMs larger than 16 Kbit.