BECKHOFF EtherCAT Technology Section I - Manual (Page 79)

Distributed Clocks
Slave Controller – Technology I-59
9.1.7 When is Synchronization established?
There are two possibilities to detect if DC synchronization of a slave is established:

Read System Time Difference (0x92C:0x092F):
If the difference is below an application specific threshold, DC has locked.
Advantage: Can be read using a single BRD command for the entire network: if the upper N bits
are zero, synchronization is established.
Recommended if an EtherCAT slave is the reference clock. If the master is the reference clock,
the threshold has to be increased to accomplish for the master jitter, which could make this
solution unusable.

Read Speed Counter Difference (0x0932:0x0933):
If the value is stable (within an application-specific range), DC has locked.
Disadvantage: Loss of lock is recognized late.
9.1.8 Clock Synchronization Initialization Example
The initialization procedure of clock synchronization including propagation delay measurement, offset
compensation, filter reset, and drift compensation is shown in the following. After initialization, all DC
slaves are synchronized with the Reference Clock.
1. Master reads the DL Status register of all slaves and calculates the network topology.
2. Master sends a broadcast write to Receive Time Port 0 register (at least first byte). All slaves latch
the local time of the first preamble bit of this frame at all ports and at the ECAT Processing Unit.
Some ESCs need the EtherCAT network to be free of frames before the broadcast write is sent.
3. Master waits until the broadcast write frame has returned.
4. Master reads all Receive Time Port 0-3 registers (depending on the topology and the Receive
Time ECAT Processing Unit register (0x0918:0x091F) which contains the upper 32 bits of the
receive times.
5. Master calculates individual propagation delays and writes them to System Time Delay registers
of the slaves. Possible overruns of the 32 bit Receive Times have to be checked and taken into
account.
6. Master sets System Time Offset register of the Reference Clock so that the Reference Clock is
bound to the master time. The offset for the Reference Clock is master time minus Receive Time
ECAT Processing Unit (local time) of the Reference Clock.
7. Master calculates System Time offsets for all DC slaves and writes them to the System Time
Offset registers. The offset of each slave is Receive Time ECAT Processing Unit from Reference
Clock minus Receive Time ECAT Processing Unit from each DC slave.
8. Master resets all slaves’s Time Control Loop filters by writing to the Speed Counter Start register
(0x0930:0x0931).
9. For static drift compensation, the master sends many separate ARMW or FRMW drift
compensation frames (e.g., 15,000 frames) to distribute the System Time of the Reference Clock
to all DC slaves.
10. For dynamic drift compensation, the master sends ARMW or FRMW commands periodically to
distribute the System Time of the Reverence Clock to all DC slaves. The rate of the drift
compensation commands depends on the acceptable maximum deviation.