BECKHOFF EtherCAT Technology Section I - Manual (Page 39)

Physical Layer Common Features
Slave Controller – Technology I-19
4.3 FIFO Size Reduction
The ESCs incorporate a receive FIFO (RX FIFO) for decoupling receive clock and processing clock.
The FIFO size is programmable by the EtherCAT master (ESC DL Control register 0x0100). Some
ESCs support a default value for the FIFO size loaded from the SII EEPROM.
The FIFO size values determine a reduction of the FIFO size, the FIFO cannot be disabled
completely. The FIFO size can be reduced considering these three factors:

Accuracy of the receiver’s clock source

Accuracy of the sender’s clock source

Maximum frame size
The default FIFO size is sufficient for maximum Ethernet Frames and default Ethernet clock source
accuracy (100 ppm). If the clock accuracy is 25 ppm or better, the FIFO size can be reduced to the
minimum. If the FIFO size was accidentally reduced too much, a short 64 Byte frame should be sent
for resetting the FIFO size to the default value, since a smaller frame is not utilizing the FIFO as much
as a larger frame.
The FIFO size can be reduced to minimum if both sender and receiver have 25 ppm accuracy of their
clock sources, even with maximum frame size.
Since 25 ppm clock accuracy can typically not be guaranteed for the entire life-time of a clock source,
the actual clock deviation has to be measured on a regular basis for FIFO size reduction. If a slave
does not support Distributed Clocks or the actual deviation is larger than 25 ppm, the FIFO size of all
neighbors and the slave itself cannot be reduced. The actual deviation can be measured using
Distributed Clocks:

Compare DC Receive Times over a period of time for slaves which only support DC Receive
Times. Do not use this method if both slaves which are compared support DC Time Loop, since
the measured deviation will approximate zero if the DC control loop has settled, but the actual
deviation determining the FIFO size might be larger than 25 ppm.

Compare calculated deviation from register Speed Counter Diff (0x0932:0x0933) for adjacent
slaves with DC Time Loop support after the DC control loop has settled (i.e., System Time
Difference 0x092C:0x092F is at its minimum).
NOTE: Be careful with FIFO size reduction at the first slave if off-the-shelf network interface cards without 25 ppm
accuracy are used by master.
Table 12: Registers for FIFO Size Reduction
Register Address Name Description
0x0100[18:16] ESC DL Control Current FIFO size setting
NOTE: Some of these register bits are set via SII EEPROM. Some of the registers are not available in specific
ESCs. Refer to Section II and III for details.
4.4 Frame Error Detection
Refer to chapter 14 (Error Counters) for details on frame error detection.