BECKHOFF EtherCAT Technology Section I - Manual (Page 46)

Ethernet Physical Layer
I-26 Slave Controller – Technology
5.10 MII Management Interface (MI)
Most EtherCAT slave controllers with MII/RMII/RGMII ports use the MII management interface for
communication with the Ethernet PHYs. The MII management interface can be used by the EtherCAT
master
– or the local µController if supported by the ESC. Enhanced MII link detection uses the
management interface for configuration and restarting auto negotiation after communication errors
occurred (TX PHYs only). Some ESCs can make use of the MII management interface for link
detection and PHY configuration. For fast link detection, the ESCs require to use a separate signal
(LINK_MII).
Refer to chapter 5.6 for details about link detection with Ethernet PHYs. For more details about the MII
management interface, refer to IEEE Standard 802.3 (Clause 22), available from the IEEE.
The ESCs support a shared MII Management Interface for all PHYs, i.e., MCLK and MDIO are
connected to the ESC and to all PHYs.
5.10.1 PHY Addressing/PHY Address Offset
Proper PHY address configuration is crucial for Enhanced Link Detection and MI Link Detection and
configuration, because the ESC itself needs to relate logical ports to the corresponding PHY
addresses. The EtherCAT master can access the Ethernet PHYs using any address by means of the
PHY address register 0x0513.
Typically, the logical port numbers match with the PHY addresses, i.e. the EtherCAT master and the
ESC itself use PHY address 0 for accessing the PHY at port 0 (PHY address 1 for the PHY at port 1
and so on).
Depending on the ESC, there are two options for configuring the PHY addresses:

PHY address offset:
The ESC accesses a PHY at logical port x with the
address “x + PHY address offset”. Depending
on the ESC only some or all possible offsets are configurable.
The EtherCAT master uses the PHY addresses 0-3 to access the logical ports 0-3. These
addresses are incremented by the PHY address offset inside the ESC. If the master uses PHY
addresses 4-31, these addresses are also incremented by the PHY address offset inside the ESC.

Individual PHY address:
The ESC accesses a PHY at each logical port with an individual PHY address.
The EtherCAT master uses the PHY addresses 0-3 to access the logical ports 0-3. These
addresses are replaced with the individual addresses inside the ESC. If the master uses PHY
addresses 4-31, these addresses are not translated.
Depending on the ESC the PHY address configuration is a strapped at power-up, configured in
advance (IP Core) or configured by signals.
Typically, the PHY address offset should be 0, and the logical port numbers match with the PHY
addresses. Some Ethernet PHYs associate a special function with PHY address 0, e.g., address 0 is a
broadcast PHY address. In these cases, PHY address 0 cannot be used. Instead, a PHY address
offset different from 0 should be selected, preferably an offset which is supported by the ESC. If PHY
addresses are chosen which are not supported by the ESC, Enhanced Link Detection and MI Link
Detection and Configuration cannot be used and have to be disabled (the PHY address offset should
be 0 in these cases). Nevertheless, the EtherCAT master can communicate with the PHYs using the
actual PHY addresses, and EtherCAT communication is possible anyway
– using the LINK_MII signal.
It is recommended that the PHY addresses are selected to be equal to the logical port number plus 1
in this case. If port 0 is EBUS, ports 1-3 should have PHY addresses 1-3, i.e., PHY address offset is 0.
If the PHY address offset configuration of an ESC reflects the actual PHY address settings, the
EtherCAT master can use addresses 0-3 in PHY address register 0x0513 for accessing the PHYs of
logical ports 0-3, regardless of the PHY address offset.