BECKHOFF EtherCAT Technology Section I - Manual (Page 23)

EtherCAT Slave Controller Overview
Slave Controller – Technology I-3
Memory
An EtherCAT slave can have an address space of up to 64Kbyte. The first block of 4 Kbyte (0x0000-
0x0FFF) is used for registers and user memory. The memory space from address 0x1000 onwards is
used as the process memory (up to 60 Kbyte). The size of process memory depends on the device.
The ESC address range is directly addressable by the EtherCAT master and an attached µController.
Process Data Interface (PDI) or Application Interface
There are several types of PDIs available, depending on the ESC:

Digital I/O (8-32 bit, unidirectional/bidirectional, with DC support)

SPI slave

8/16 bit µController (asynchronous or synchronous)

On-chip bus (e.g., Avalon ® , PLB ® , or AXI ® , depending on target FPGA type and selection)

General purpose I/O
The PDIs are described in Section III of the particular ESC, since the PDI functions are highly
depending on the ESC type.
SII EEPROM
One non-volatile memory is needed for EtherCAT Slave Information (ESI) storage, typically an I²C
EEPROM. If the ESC is implemented as an FPGA, a second non-volatile memory is necessary for the
FPGA configuration code.
Status / LEDs
The Status block provides ESC and application status information. It controls external LEDs like the
application RUN LED/ERR LED and port Link/Activity LEDs.
1.2 Further Reading on EtherCAT and ESCs
For further information on EtherCAT, refer to the EtherCAT specification ETG.1000, available from the
EtherCAT Technology Group (ETG,
http://www.ethercat.org ), and the IEC standard “Digital data
communications for measurement and control – Fieldbus for use in industrial control systems”, IEC
61158 Type 12: EtherCAT, available from the IEC ( http://www.iec.ch ).
Additional documents on EtherCAT can be found on the EtherCAT Technology Group website
(
http://www.ethercat.org ).
Documentation on Beckhoff Automation EtherCAT Slave Controllers is available at the Beckhoff
website (
http://www.beckhoff.com ), e.g., data sheets, application notes, and ASIC pinout configuration
tools.
1.3 Scope of Section I
Section I deals with the basic EtherCAT technology. Starting with the EtherCAT protocol itself, the
frame processing inside EtherCAT slaves is described. The features and interfaces of the physical
layer with its two alternatives Ethernet and EBUS are explained afterwards. Finally, the details of the
functional units of an ESC like FMMU, SyncManager, Distributed Clocks, Slave Information Interface,
Interrupts, Watchdogs, and so on, are described.
Since Section I is common for all Beckhoff ESCs, it contains features which might not be available in
every individual ESC. Refer to the feature details overview in Section III of a specific ESC to find out
which features are actually available.
The following Beckhoff ESCs are covered by Section I:

ET1200-0003

ET1100-0003

EtherCAT IP Core for Altera ® FPGAs (V3.0.6)

EtherCAT IP Core for Xilinx ® FPGAs (V3.00g)

ESC20 (Build 22)