FIGURES
I-XII
Slave Controller
– Technology
Figure 1: EtherCAT Slave Controller Block Diagram .............................................................................. 1
Figure 2: Ethernet Frame with EtherCAT Data ....................................................................................... 4
Figure 3: EtherCAT Datagram ................................................................................................................. 5
Figure 4: Auto close loop state transitions ............................................................................................ 13
Figure 5: Frame Processing .................................................................................................................. 14
Figure 6: Circulating Frames ................................................................................................................. 15
Figure 7: All frames are dropped because of Circulating Frame Prevention ........................................ 16
Figure 8: Write access ........................................................................................................................... 29
Figure 9: Read access ........................................................................................................................... 29
Figure 10: MII management example schematic .................................................................................. 30
Figure 11: Termination and Grounding Recommendation .................................................................... 31
Figure 12: RJ45 Connector ................................................................................................................... 32
Figure 13: M12 D-code Connector ........................................................................................................ 32
Figure 14: Back-to-Back MII Connection (two ESCs) ........................................................................... 33
Figure 15: Back-to-Back MII Connection (ESC and standard MAC)..................................................... 34
Figure 16: EBUS Interface Signals ........................................................................................................ 35
Figure 17: EBUS Protocol ..................................................................................................................... 36
Figure 18: Example EtherCAT Network ................................................................................................ 37
Figure 19: EBUS Connection ................................................................................................................ 38
Figure 20: FMMU Mapping Principle ..................................................................................................... 39
Figure 21: FMMU Mapping Example ..................................................................................................... 40
Figure 22: SyncManager Buffer allocation ............................................................................................ 42
Figure 23: SyncManager Buffered Mode Interaction............................................................................. 42
Figure 24: SyncManager Mailbox Interaction ........................................................................................ 43
Figure 25: EtherCAT Mailbox Header (for all Types) ............................................................................ 44
Figure 26: Handling of a Repeat Request with Read Mailbox .............................................................. 46
Figure 27: Propagation Delay, Offset, and Drift Compensation ............................................................ 49
Figure 28: Propagation Delay Calculation ............................................................................................. 52
Figure 29: Distributed Clocks signals .................................................................................................... 60
Figure 30: SyncSignal Generation Modes ............................................................................................. 61
Figure 31: SYNC0/1 Cycle Time Examples .......................................................................................... 63
Figure 32: System Time PDI Controlled with three steps ..................................................................... 66
Figure 33: System Time PDI Controlled with two steps ........................................................................ 67
Figure 34: DC Timing Signals in relation to Communication ................................................................. 68
Figure 35: EtherCAT State Machine ..................................................................................................... 70
Figure 36: SII EEPROM Layout............................................................................................................. 72
Figure 37: I²C EEPROM signals ............................................................................................................ 78
Figure 38: Write access (1 address byte, up to 16 Kbit EEPROMs) ..................................................... 80
Figure 39: Write access (2 address bytes, 32 Kbit - 4 Mbit EEPROMs) ............................................... 81
Figure 40: Read access (1 address byte, up to 16 Kbit EEPROMs) .................................................... 81
Figure 41: PDI Interrupt Masking and interrupt signals ......................................................................... 82
Figure 42: ECAT Interrupt Masking ....................................................................................................... 83
