BECKHOFF EtherCAT Technology Section I - Manual (Page 86)

Distributed Clocks
I-66 Slave Controller – Technology
9.3 System Time PDI Controlled
Sometimes Distributed Clocks of different EtherCAT networks have to be synchronized. One solution
is master-master communication, the other one is based on a physical device which is present in both
EtherCAT networks. One of the networks contains the DC Reference Clock (DC source), the other
one
– DC destination – is synchronized to the Reference Clock in the DC source network.
Some ESCs support such a synchronization by a different functionality of the System Time register
(0x0910:0x0913). In normal operation mode, a write access initiated by the EtherCAT master to the
System Time register triggers the synchronization: the written value is compared to the local copy of
the System Time, and the difference is fed into the control loop. If the System Time is PDI controlled,
the PDI writes the System Time register, and the written value is compared to the DC Latch0 Time
Positive Edge register (0x09B0:0x09B3). This feature makes the accuracy of the synchronization
independent of the µController/PDI response times.
The following figures illustrate how the System Time is transferred from the DC source to the DC
destination. ESC 1 and ESC 2 are located in different EtherCAT networks. The EtherCAT network of
ESC 1 contains the Reference Clock, the network of ESC 2 will become synchronized to this
Reference Clock.
ESC 2 is the “reference clock” of its EtherCAT network. There are two options for
synchronization, which has to be performed on a regular basis.
The first option is to let the µController generate a trigger pulse for ESC 1 and 2. The time of the rising
edge is stored in the Latch0 Time Positive Edge register both in ESC 1 and 2. Afterwards, the
µController reads this time from ESC 1 and writes it into the System Time register of ESC 2. The
difference of the Latch0 times is used to feed the control loop.
Output
µC generates
rising edge for
ESC 1 & 2
µC reads Latch0 Time pos. edge
from ESC 1
µC writes Latch0 Time pos. edge
from ESC 1 to System Time
register of ESC 2
1
3 2
ESC 1
DC source
ESC 2
DC
destination
µController
L
a
tc
h
0
L
a
tc
h
0
Figure 32: System Time PDI Controlled with three steps