Avago Technologies LSI53C1000R - Manual (Page 15)

xv
Version 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.
Tables
2.1 PCI Bus Commands and Encoding Types 2-5
2.2 PCI Cache Mode Alignment 2-11
2.3 New Phases on SCSI Bus 2-23
2.4 Bits Used for Parity/CRC/AIP Control and Generation 2-34
2.5 SCSI Parity Errors and Interrupts 2-36
2.6 SCF Divisor Values 2-42
2.7 Parallel ROM Support 2-59
2.8 Default Download Mode Serial EEPROM Data Format 2-61
2.9 Power States 2-62
3.1 LSI53C1000R Internal Pull-ups and Pull-downs 3-4
3.2 System Signals 3-5
3.3 Address and Data Signals 3-6
3.4 Interface Control Signals 3-7
3.5 Arbitration Signals 3-8
3.6 Error Reporting Signals 3-9
3.7 Interrupt Signals 3-9
3.8 SCSI Bus Interface Signals 3-10
3.9 SCSI Signals 3-10
3.10 SCSI Control Signals 3-12
3.11 GPIO Signals 3-13
3.12 Flash ROM and Memory Interface Signals 3-14
3.13 Test Interface Signals 3-15
3.14 Power and Ground Signals 3-16
3.15 MAD[3:1] Pin Decoding 3-18
4.1 PCI Configuration Register Map 4-2
4.2 SCSI Register Map 4-22
4.3 Maximum Synchronous Offset 4-34
4.4 DT Transfer Rates 4-107
4.5 Single Transition Transfer Rates 4-110
5.1 Read/Write Instructions 5-25
6.1 Absolute Maximum Stress Ratings 6-2
6.2 Operating Conditions 6-2
6.3 LVD Driver SCSI Signals – SD[15:0], SDP[1:0], SREQ/,
SACK/, SMSG/, SIO/, SCD/, SATN/, SBSY/, SSEL/, SRST/
6-3
6.4 LVD Receiver SCSI Signals – SD[15:0], SDP[1:0], SREQ/,
SACK/, SMSG/, SIO/, SCD/, SATN/, SBSY/, SSEL/, SRST/
6-3