Avago Technologies LSI53C1000R - Manual (Page 264)

5-22 SCSI SCRIPTS Instruction Set
Version 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.
R Reserved [5:4]
ATN Set/Clear SATN/ 3
This bit is used in conjunction with a Set or Clear
instruction to assert or deassert SATN/.
The Set instruction asserts SATN/ on the SCSI bus. The
Clear instruction deasserts SATN/ on the SCSI bus. The
corresponding bit in the
SCSI Output Control Latch (SOCL)
register are set or cleared depending on the instruction
used. Because SATN/ is an initiator signal, it is not
asserted on the SCSI bus unless the LSI53C1000R is
operating as an initiator.
The Set/Clear SCSI ACK/, ATN/ instructions are used after
message phase Block Move operations to give the initiator
the opportunity to assert attention before acknowledging
the last message byte. For example, if the initiator wishes
to reject a message, it issues an Assert SCSI ATN
instruction before a Clear SCSI ACK instruction.
R Reserved [2:0]
5.3.2 Second Dword
This section describes the second Dword of the I/O Instruction register.
Figure 5.6 Second 32-Bit Word of the I/O Instruction
SA Start Address [31:0]
This 32-bit field contains the memory address to fetch the
next instruction if the selection or reselection fails.
If relative or table relative addressing is used, this value
is a 24-bit signed offset relative to the current
DMA SCRIPTS Pointer (DSP) register value.
31 0
DSPS Register