Avago Technologies LSI53C1000R - Manual (Page 370)

B-2 External Memory Interface Diagram Examples
Version 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.
Figure B.2 64 Kbyte Interface with 150 ns Memory
27C512-15/
MOE/
OE
MCE/
CE
Note: MAD 3, 1, 0 pulled LOW internally. MAD bus sense logic enabled for 64 Kbytes of fast memory
(150 ns devices @ 66 MHz).
GPIO4
MWE/
+ 12 V VPP
WE
Optional – for Flash Memory only,
not required for EEPROMs.
28F512-15/
Socket
LSI53C1000R
D[7:0]
CK
Q[7:0]
A[7:0]
QE
D[7:0]
CK
Q[7:0]
QE
A[15:8]
8
V
DD
MAS0/
MAS1/
8
HCT374
HCT374
D[7:0]
MAD2 4.7 K
8
8
VPP
Control
MAD[7:0]
Bus