Avago Technologies LSI53C1000R - Manual (Page 97)

Signal Organization 3-3
Version 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.
Figure 3.1 LSI53C1000R Signal Grouping
CLK
RST/
AD[63:0]
C_BE[7:0]/
PAR
PAR64
ACK64/
REQ64/
FRAME/
TRDY/
IRDY/
STOP/
DEVSEL/
IDSEL
REQ/
GNT/
PERR/
SERR/
GPIO0_FETCH/
GPIO1_MASTER/
GPIO2
GPIO3
GPIO4
MWE/
MCE/
MOE/_TESTOUT
MAS0/
MAS1/
MAD[7:0]
SCLK
SD[15:0]/
SDP[1:0]/
SC_D/
SI_O/
SMSG/
SREQ/
SBSY/
SATN/
SRST/
SSEL/
TEST_RST/
TEST_HSC
MOE/_TESTOUT
TCK
TMS
TDI
TDO
DIFFSENS
LSI53C1000R
Interface
SCSI
Bus
Interface
System
Address
and
Data
Interface
Control
Arbitration
Error
Reporting
GPIO
Flash
ROM
and
Memory
Interface
PCI
Bus
Interface
SACK/
TEST_PD
SCAN_MODE
ENABLE66
M66EN
INTA/
ALT_INTA/
INT_DIR
Interrupt
Interface
Test