Avago Technologies LSI53C1000R - Manual (Page 188)

4-76 Registers
Version 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.
Register: 0x43
SCSI Interrupt Status One (SIST1)
Read Only
Reading the SIST1 register returns the status of the various interrupt
conditions, whether they are enabled in the
SCSI Interrupt Enable One (SIEN1) register or not. Each bit set indicates
an occurrence of the corresponding condition. Reading the SIST1 clears
the interrupt condition.
R Reserved [7:5]
SBMC SCSI Bus Mode Change 4
This bit is set when the DIFFSENS pin detects a change
in voltage level indicating the SCSI bus has switched
between SE, LVD, or HVD modes. HVD is not supported.
R Reserved 3
STO Selection or Reselection Time-Out 2
This bit is set when the SCSI device which the
LSI53C1000R is attempting to select or reselect does not
respond within the programmed time-out period. Refer to
the description of the
SCSI Timer Zero (STIME0) register,
bits [3:0], for more information on the time-out timer.
GEN General Purpose Timer Expired 1
This bit is set when the general purpose timer expires.
The time measured is the time between enabling and
disabling of the timer. Refer to the description of the
SCSI Timer One (STIME1) register, bits [3:0], for more
information on the general purpose timer.
HTH Handshake-to-Handshake Timer Expired 0
This bit is set when the handshake-to-handshake timer
expires. The time measured is the SCSI
Request-to-Request (target) or
Acknowledge-to-Acknowledge (initiator) period. Refer to
the description of the
SCSI Timer Zero (STIME0) register,
bits [7:4], for more information on the
handshake-to-handshake timer.
7 5 4 3 2 1 0
R SBMC R STO GEN HTH
0 0 0 0 0 0 0 0