Avago Technologies LSI53C1000R - Manual (Page 319)

PCI and External Memory Interface Timing Diagrams 6-37
Version 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.
Figure 6.23 Burst Write, 32-Bit Address and Data
t
1
CLK
(Driven by System)
GPIO0_FETCH/
(Driven by LSI53C1000R)
GPIO1_MASTER/
(Driven by LSI53C1000R)
REQ/
(Driven by LSI53C1000R)
PAR
(Driven by LSI53C1000R)
IRDY/
(Driven by LSI53C1000R)
TRDY/
(Driven by Target)
STOP/
(Driven by Target)
DEVSEL/
(Driven by Target)
AD[31:0]
(Driven by LSI53C1000R)
C_BE[3:0]/
(Driven by LSI53C1000R)
t
3
CMD
GNT/
(Driven by Arbiter)
FRAME/
(Driven by LSI53C1000R)
Addr
Out
t
2
BE
Data
Out
Data
Out
t
1
t
2