Avago Technologies LSI53C1000R - Manual (Page 383)

Index IX-11
instruction type 5-14
opcode 5-14
relative addressing mode 5-18
select with ATN/ 5-20
set/clear carry 5-21
set/clear SACK/ 5-21
set/clear SATN/ 5-22
set/clear target mode 5-21
start address 5-22
table indirect mode 5-19
I/O instructions 5-14
instruction prefetch 2-31
internal RAM 2-20
interrupt instruction 5-29
interrupt instruction received (SIR) 4-40 , 4-65
interrupt on the fly instruction 5-29
jump instruction 5-27
load and store
byte count 5-40
DSA relative 5-39
instruction type 5-39
instructions 2-33
load/store 5-39
memory I/O address and DSA offset 5-40
no flush 5-39
register address 5-40
memory move
DSPS register 5-36
instruction type 5-35
no flush 5-35
TEMP register 5-37
transfer count 5-35
operation 5-1
overview 5-4
phase mismatch handling 2-19
processor 2-19
internal RAM for instruction storage 2-20
performance 2-19
RAM 2-4 , 2-20
read/write
A[6:0] 5-24
destination address 5-24
immediate data 5-24
instruction type 5-23
opcode 5-23
operator 5-23
upper register address line [A7] 5-24
use data8/SFBR 5-23
reselect instruction 5-15
return instruction 5-28
running (SRUN) 4-50
select instruction 5-17
set instruction 5-16 , 5-18
transfer control
32/64-bit jump 5-31
carry test 5-31
compare data 5-32
compare phase 5-32
data compare mask 5-32
data compare value 5-33
instruction type 5-27
interrupt-on-the-fly 5-31
jump address 5-33
jump if true/false 5-31
jump64 address 5-33
opcode 5-27
relative addressing 5-30
SCSI Phase 5-29
wait for valid phase 5-32
wait disconnect instruction 5-17
wait select instruction 5-15
SCSI
activity LED 2-21
asynchronous receive 2-38
asynchronous send 2-37
ATN condition - target mode (M/A) 4-69
bit mode change (SBMC) 4-76
bus control lines (SBCL) 4-38
bus data lines (SBDL) 4-94
bus interface 2-39 , 2-41
bus mode change (SBMC) 4-72
byte count (SBC) 4-119
C_D/ signal (C_D) 4-44
chip ID (SCID) 4-32
clock 3-10
clock quadrupler 2-31
control enable (SCE) 4-86
control four (SCNTL4) 2-42
control one (SCNTL1) 2-34 , 4-27
control three (SCNTL3) 2-42 , 4-31
control two (SCNTL2) 4-29
control zero (SCNTL0) 2-34 , 4-23
cumulative byte count 4-120
destination ID (SDID) 4-34
disconnect unexpected (SDU) 4-29
encoded destination ID 5-21
first byte received (SFBR) 4-36
function A GPIO signals 3-13
functional description 2-18
gross error (SGE) 4-70 , 4-74
hysteresis of receivers 6-9
I/O instructions 5-14
I_O/ signal (I_O) 4-44
input data latch (SIDL) 4-89
input filtering 6-8
instructions