Avago Technologies LSI53C1000R - Manual (Page 220)

4-108 Registers
Version 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.
160 4 0 25.00 20.00 20.00
160 4 1 25.00 20.00 16.00
160 4 2 25.00 20.00 13.33
160 4 3 25.00 20.00 11.43
160 4 4 25.00 20.00 10.00
160 6 0 37.50 13.33 13.33
160 6 1 37.50 13.33 10.67
160 6 2 37.50 13.33 8.89
160 6 3 37.50 13.33 7.62
160 6 4 37.50 13.33 6.67
160 8 0 50.00 10.00 10.00
160 8 1 50.00 10.00 8.00
160 8 2 50.00 10.00 6.67
160 8 3 50.00 10.00 5.71
160 8 4 50.00 10.00 5.00
40 1 0 25.00 20.00 20.00
40 1 1 25.00 20.00 16.00
40 1 2 25.00 20.00 13.33
40 1 3 25.00 20.00 11.43
40 1 4 25.00 20.00 10.00
Table 4.4 DT Transfer Rates (Cont.)
Clock
(MHz)
Divisor
Number
Xclks
1
Base
Period
(ns)
Receive Rate
(Megatransfers/)
Send Rate
(Megatransfers/)