Avago Technologies LSI53C1000R - Manual (Page 255)

Block Move Instructions 5-13
Version 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.
TC[23:0] Transfer Counter [23:0]
This 24-bit field specifies the number of data bytes to be
moved between the LSI53C1000R and system memory.
The field is stored in the
DMA Byte Counter (DBC) register.
When the LSI53C1000R transfers data to/from memory,
the DBC register is decremented by the number of bytes
transferred. In addition, the
DMA Next Address (DNAD)
register is incremented by the number of bytes transferred.
This process is repeated until the DBC register is
decremented to zero. At this time, the LSI53C1000R
fetches the next instruction.
If bit 28 is set, indicating table indirect addressing, this field
is not used. The byte count is instead fetched from a table
pointed to by the
Data Structure Address (DSA) register.
5.2.2 Second Dword
This section describes the structure of the second SCSI SCRIPTS block
move instruction Dword.
Figure 5.3 Block Move Instruction – Second Dword
Start Address [31:0]
This 32-bit field specifies the starting address of the data
to move to/from memory. This field is copied to the
DMA Next Address (DNAD) register. When the
LSI53C1000R transfers data to or from memory, the
DNAD register is incremented by the number of bytes
transferred.
When bit 29 is set, indicating indirect addressing, this
address is a pointer to an address in memory that points
to the data location. When bit 28 is set, indicating table
indirect addressing, the value in this field is an offset into
a table pointed to by the
Data Structure Address (DSA) .
The table entry contains byte count and address
information.
31 0
DSPS Register