Avago Technologies LSI53C1000R - Manual (Page 253)

Block Move Instructions 5-11
Version 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.
the LSI53C1000R stores the last byte in the
SCSI Wide Residue (SWIDE) register during a receive
operation. This byte is combined with the first byte from
the subsequent transfer so that a wide transfer can
complete.
If the SATN/ signal is asserted by the initiator or a parity
error occurred during the transfer, it is possible to halt the
transfer and generate an interrupt. The Disable Halt on
Parity Error or ATN bit in the
SCSI Control One (SCNTL1)
register controls whether the LSI53C1000R halts on
these conditions immediately, or waits until completion of
the current Move.
Initiator Mode
The LSI53C1000R verifies that it is connected to the
SCSI bus as an initiator before executing this instruction.
The LSI53C1000R waits for an unserviced phase to
occur. An unserviced phase is defined as any phase
(with SREQ/ asserted) for which the LSI53C1000R has
not yet transferred data by responding with a SACK/.
The LSI53C1000R compares the SCSI phase bits in the
DMA Command (DCMD) register with the latched SCSI
phase lines stored in the SCSI Status One (SSTAT1)
register. These phase lines are latched when SREQ/ is
asserted.
If the SCSI phase bits match the value stored in the
SCSI Status One (SSTAT1) register, the LSI53C1000R
transfers the number of bytes specified in the
DMA Byte Counter (DBC) register starting at the address
pointed to by the DMA Next Address (DNAD) register. If the
opcode bit is cleared and a data transfer ends on an odd
byte boundary, the LSI53C1000R stores the last byte in the
SCSI Wide Residue (SWIDE) register during a receive
operation, or in the SCSI Output Data Latch (SODL)
register during a send operation. This byte is combined
with the first byte from the subsequent transfer so that a
wide transfer can complete.
OPC Instruction Defined
0 CHMOV/CHMOV64
1 MOVE/MOVE64