1 target timing, Target timing – Avago Technologies LSI53C1000R User Manual

Page 297

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background image

PCI and External Memory Interface Timing Diagrams

6-15

Version 2.2

Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.

–

Normal/Fast Memory ( 128 Kbytes) Single Byte Access Read
Cycle

–

Normal/Fast Memory ( 128 Kbytes) Single Byte Access Write
Cycle

–

Normal/Fast Memory ( 128 Kbytes) Multiple Byte Access Read
Cycle

–

Normal/Fast Memory ( 128 Kbytes) Multiple Byte Access Write
Cycle

–

Slow Memory ( 128 Kbytes) Read Cycle

–

Slow Memory ( 128 Kbytes) Write Cycle

–

≤

64 Kbytes ROM Read Cycle

–

≤

64 Kbytes ROM Write Cycle

6.4.1 Target Timing

Tables

6.17

through

6.22

and Figures

6.11

through

6.16

describe Target

timing.

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