Avago Technologies LSI53C1000R - Manual (Page 44)

2-14 Functional Description
Version 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.
2.1.3.5 Examples
The examples in this section employ the following abbreviations:
MR = Memory Read; MRL = Memory Read Line; MRM = Memory Read
Multiple; MW = Memory Write; MWI = Memory Write and Invalidate.
Read Example 1 – Burst = 4 Dwords; Cache Line Size = 4 Dwords:
A to B: MRL (6 bytes)
A to C: MRL (13 bytes)
A to D: MRM (16 bytes)
MR (1 byte)
C to D: MRM (5 bytes)
C to E: MRM (16 bytes)
MRM (5 bytes)
D to F: MRM (16 bytes)
MRM (16 bytes)
A to H: MRM (16 bytes)
MRM (16 bytes)
MRM (16 bytes)
MRM (16 bytes)
MRM (16 bytes)
MR (1 byte)
A to G: MRM (16 bytes)
MRM (16 bytes)
MRM (16 bytes)
MRM (16 bytes)
MR (2 bytes)